Abstract
This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.
Original language | English (US) |
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Pages (from-to) | 289-294 |
Number of pages | 6 |
Journal | Proceedings of the International Symposium on Low Power Electronics and Design |
State | Published - Dec 3 2000 |