Analysis and design of low-phase-noise ring oscillators

Liang Dai, Ramesh Harjani

Research output: Contribution to journalArticlepeer-review

11 Scopus citations


This paper presents a framework for CMOS ring oscillator phase noise analysis for given power consumption specifications. This model considers both linear and nonlinear operations. It indicates that fast rail-to-rail switching has to be achieved for low phase noise and that the up-conversion of low-frequency noise from the current bias/control circuit can be significant. Our phase noise model is validated via simulation and measurement results. We also present a coupled-ring oscillator whose phase noise is -114 dBc/Hz at a 600 kHz offset from the 960 MHz carrier frequency.

Original languageEnglish (US)
Pages (from-to)289-294
Number of pages6
JournalProceedings of the International Symposium on Low Power Electronics and Design
StatePublished - Dec 3 2000


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