Analysis and design of energy-efficient data-dependent SRAM

Wenfeng Zhao, Ang Li, Yi Wang, Yajun Ha

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Scopus citations


Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technonology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.

Original languageEnglish (US)
Title of host publicationProceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
EditorsYajie Qin, Zhiliang Hong, Ting-Ao Tang
PublisherIEEE Computer Society
Number of pages4
ISBN (Electronic)9781509066247
StatePublished - Jul 1 2017
Event12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China
Duration: Oct 25 2017Oct 28 2017

Publication series

NameProceedings of International Conference on ASIC
ISSN (Print)2162-7541
ISSN (Electronic)2162-755X


Other12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017

Bibliographical note

Funding Information:
VIII. ACKNOWLEDGEMENT This work is sponsored by ShanghaiTech University research start-up grant F-0203-17-003

Publisher Copyright:
© 2017 IEEE.


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