Analysis and design of energy-efficient data-dependent SRAM

Wenfeng Zhao; Ang Li; Yi Wang; Yajun Ha

doi:10.1109/ASICON.2017.8252625

Analysis and design of energy-efficient data-dependent SRAM

Wenfeng Zhao, Ang Li, Yi Wang, Yajun Ha

Biomedical Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

1 Scopus citations

Abstract

Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technonology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.

Original language	English (US)
Title of host publication	Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017
Editors	Yajie Qin, Zhiliang Hong, Ting-Ao Tang
Publisher	IEEE Computer Society
Pages	912-915
Number of pages	4
ISBN (Electronic)	9781509066247
DOIs	https://doi.org/10.1109/ASICON.2017.8252625
State	Published - Jul 1 2017
Event	12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China Duration: Oct 25 2017 → Oct 28 2017

Publication series

Name	Proceedings of International Conference on ASIC
Volume	2017-October
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Other

Other	12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017
Country/Territory	China
City	Guiyang
Period	10/25/17 → 10/28/17

Bibliographical note

Funding Information:
VIII. ACKNOWLEDGEMENT This work is sponsored by ShanghaiTech University research start-up grant F-0203-17-003

Publisher Copyright:
© 2017 IEEE.

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

Publisher link

10.1109/ASICON.2017.8252625

Find It

Find It at U of M Libraries

Cite this

Zhao, W., Li, A., Wang, Y., & Ha, Y. (2017). Analysis and design of energy-efficient data-dependent SRAM. In Y. Qin, Z. Hong, & T-A. Tang (Eds.), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017 (pp. 912-915). (Proceedings of International Conference on ASIC; Vol. 2017-October). IEEE Computer Society. https://doi.org/10.1109/ASICON.2017.8252625

Analysis and design of energy-efficient data-dependent SRAM. / Zhao, Wenfeng; Li, Ang; Wang, Yi et al.
Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. ed. / Yajie Qin; Zhiliang Hong; Ting-Ao Tang. IEEE Computer Society, 2017. p. 912-915 (Proceedings of International Conference on ASIC; Vol. 2017-October).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Zhao, W, Li, A, Wang, Y & Ha, Y 2017, Analysis and design of energy-efficient data-dependent SRAM. in Y Qin, Z Hong & T-A Tang (eds), Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017. Proceedings of International Conference on ASIC, vol. 2017-October, IEEE Computer Society, pp. 912-915, 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017, Guiyang, China, 10/25/17. https://doi.org/10.1109/ASICON.2017.8252625

@inproceedings{5e9c97fd5dd040468bfdf2c968a9a516,

title = "Analysis and design of energy-efficient data-dependent SRAM",

abstract = "Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technonology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.",

author = "Wenfeng Zhao and Ang Li and Yi Wang and Yajun Ha",

note = "Funding Information: VIII. ACKNOWLEDGEMENT This work is sponsored by ShanghaiTech University research start-up grant F-0203-17-003 Publisher Copyright: {\textcopyright} 2017 IEEE.; 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 ; Conference date: 25-10-2017 Through 28-10-2017",

year = "2017",

month = jul,

day = "1",

doi = "10.1109/ASICON.2017.8252625",

language = "English (US)",

series = "Proceedings of International Conference on ASIC",

publisher = "IEEE Computer Society",

pages = "912--915",

editor = "Yajie Qin and Zhiliang Hong and Ting-Ao Tang",

booktitle = "Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017",

}

TY - GEN

T1 - Analysis and design of energy-efficient data-dependent SRAM

AU - Zhao, Wenfeng

AU - Li, Ang

AU - Wang, Yi

AU - Ha, Yajun

PY - 2017/7/1

Y1 - 2017/7/1

N2 - Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technonology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.

AB - Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technonology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.

UR - http://www.scopus.com/inward/record.url?scp=85044761983&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85044761983&partnerID=8YFLogxK

U2 - 10.1109/ASICON.2017.8252625

DO - 10.1109/ASICON.2017.8252625

M3 - Conference contribution

AN - SCOPUS:85044761983

T3 - Proceedings of International Conference on ASIC

SP - 912

EP - 915

BT - Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017

A2 - Qin, Yajie

A2 - Hong, Zhiliang

A2 - Tang, Ting-Ao

PB - IEEE Computer Society

T2 - 12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017

Y2 - 25 October 2017 through 28 October 2017

ER -

Analysis and design of energy-efficient data-dependent SRAM

Abstract

Publication series

Other

Bibliographical note

UN SDGs

Publisher link

Find It

Other files and links

Fingerprint

Cite this