Improving the energy efficiency of on-chip SRAM is a crucial task in memory-intensive system designs. This paper presents design considerations and architectural exploration for energy-efficient data-dependent SRAMs, in which the power consumption depends on the data stored in the bitcells. We further categorize the data-dependent SRAM designs into two broad types, i.e., distance-based SRAM and weight-based SRAM, and point out similarities of such data-dependent power consumption mechanism between the SRAM designs and bus termination techniques. Simulation results in a commercial 40nm CMOS technonology show that when more than 50%/25% of write/read data word are bit 1, the DD-8T SRAM is more energy-efficient than the 6T SRAM. And with XNOR encoded correlated image data, DD-8T SRAM shows both decreased write (1.4× to 2.4×) and read (1.64× to 1.85×) access energy compared to 6T SRAM.
|Original language||English (US)|
|Title of host publication||Proceedings - 2017 IEEE 12th International Conference on ASIC, ASICON 2017|
|Editors||Yajie Qin, Zhiliang Hong, Ting-Ao Tang|
|Publisher||IEEE Computer Society|
|Number of pages||4|
|State||Published - Jul 1 2017|
|Event||12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017 - Guiyang, China|
Duration: Oct 25 2017 → Oct 28 2017
|Name||Proceedings of International Conference on ASIC|
|Other||12th IEEE International Conference on Advanced Semiconductor Integrated Circuits, ASICON 2017|
|Period||10/25/17 → 10/28/17|
Bibliographical noteFunding Information:
VIII. ACKNOWLEDGEMENT This work is sponsored by ShanghaiTech University research start-up grant F-0203-17-003
© 2017 IEEE.