Hierarchical analog layout generators proceed from leaf cells ('primitives') to progressively larger blocks that are placed and routed. The quality of primitive cell layout is critical for design performance. This paper proposes a methodology that defines and optimizes the performance metrics of primitives during leaf cell layout. It incorporates layout parasitics and layout-dependent effects, providing a set of optimized layout choices for use by the place-and-route engine, as well as wire sizing guidelines for connections outside the cell. For FinFET-based designs of a high-frequency amplifier, a StrongARM comparator, and a fully differential VCO, our approach outperforms existing methods and is competitive with time-intensive manual layout.
|Original language||English (US)|
|Title of host publication||Proceedings of the 2021 Design, Automation and Test in Europe, DATE 2021|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||6|
|State||Published - Feb 1 2021|
|Event||2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021 - Virtual, Online|
Duration: Feb 1 2021 → Feb 5 2021
|Name||2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)|
|Conference||2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021|
|Period||2/1/21 → 2/5/21|
Bibliographical noteFunding Information:
This work is supported in part by the DARPA IDEA program, as part of the ALIGN project, under SPAWAR Contract N660011824048. The authors would like to thank M. Hassanpourghadi and Prof. M. Chen at USC for providing the VCO circuit.
© 2021 EDAA.