Analog Layout Generation using Optimized Primitives

Meghna Madhusudan, Arvind K Sharma, Yaguang Li, Jiang Hu, Sachin S. Sapatnekar, Ramesh Hajiani

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Hierarchical analog layout generators proceed from leaf cells ('primitives') to progressively larger blocks that are placed and routed. The quality of primitive cell layout is critical for design performance. This paper proposes a methodology that defines and optimizes the performance metrics of primitives during leaf cell layout. It incorporates layout parasitics and layout-dependent effects, providing a set of optimized layout choices for use by the place-and-route engine, as well as wire sizing guidelines for connections outside the cell. For FinFET-based designs of a high-frequency amplifier, a StrongARM comparator, and a fully differential VCO, our approach outperforms existing methods and is competitive with time-intensive manual layout.

Original languageEnglish (US)
Title of host publicationProceedings of the 2021 Design, Automation and Test in Europe, DATE 2021
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages1234-1239
Number of pages6
ISBN (Electronic)9783981926354
DOIs
StatePublished - Feb 1 2021
Event2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021 - Virtual, Online
Duration: Feb 1 2021Feb 5 2021

Publication series

Name2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)

Conference

Conference2021 Design, Automation and Test in Europe Conference and Exhibition, DATE 2021
CityVirtual, Online
Period2/1/212/5/21

Bibliographical note

Funding Information:
This work is supported in part by the DARPA IDEA program, as part of the ALIGN project, under SPAWAR Contract N660011824048. The authors would like to thank M. Hassanpourghadi and Prof. M. Chen at USC for providing the VCO circuit.

Publisher Copyright:
© 2021 EDAA.

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