Analog circuit synthesis for performance in OASAYS

Ramesh Harjani, Rob A. Rutenbar, L. Richard Carley

Research output: Chapter in Book/Report/Conference proceedingConference contribution

9 Scopus citations

Abstract

Mechanisms needed to meet stringent performance demands in a hierarchically structured analog circuit synthesis tool are described. Experiences with adding a high-speed comparator design style to the OASYS synthesis tool are discussed. It is argued that design iteration--the process of making a heuristic design choice, following it through to possible failure, then diagnosing the failure and modifying the overall plan of attack for the synthesis--is essential to meet such performance demands. Examples of high-speed comparators automatically synthesized by OASYS are presented. Designs competitive in quality with manual expert designs, e.g., with response time of 6 ns and input drive of 1 mV, can be synthesized in under 5 on a workstation.

Original languageEnglish (US)
Title of host publicationIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof
PublisherPubl by IEEE
Pages492-495
Number of pages4
ISBN (Print)0818608692
StatePublished - Dec 1 1988

Publication series

NameIEEE Int Conf on Comput Aided Des ICCAD 88 a Conf for the EE CAD Prof

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