An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits

Saurabh Kumar; Minki Cho; Luke Everson; Hoonki Kim; Qianying Tang; Paul Mazanec; Pascal Meinerzhagen; Andres Malavasi; Dan Lake; Carlos Tokunaga; Muhammad Khellah; James Tschanz; Shekhar Borkar; Vivek De; Chris H. Kim

doi:10.1109/IEDM.2017.8268521

An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits

Saurabh Kumar, Minki Cho, Luke Everson, Hoonki Kim, Qianying Tang, Paul Mazanec, Pascal Meinerzhagen, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad Khellah, James Tschanz, Shekhar Borkar, Vivek De, Chris H. Kim

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

4 Scopus citations

Abstract

This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.

Original language	English (US)
Title of host publication	2017 IEEE International Electron Devices Meeting, IEDM 2017
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	39.3.1-39.3.4
ISBN (Electronic)	9781538635599
DOIs	https://doi.org/10.1109/IEDM.2017.8268521
State	Published - Jan 23 2018
Event	63rd IEEE International Electron Devices Meeting, IEDM 2017 - San Francisco, United States Duration: Dec 2 2017 → Dec 6 2017

Publication series

Name	Technical Digest - International Electron Devices Meeting, IEDM
ISSN (Print)	0163-1918

Other

Other	63rd IEEE International Electron Devices Meeting, IEDM 2017
Country/Territory	United States
City	San Francisco
Period	12/2/17 → 12/6/17

Bibliographical note

Funding Information:
Acknowledgements: The authors would like to thank Dr. Heather Quinn at Los Alamos National Labs for her help with the neutron beam tests. This work was funded in part by the U.S. Government. The data analysis work was partially supported by the Defense Threat Reduction Agency under Basic Research Award No. HDTRA1-14-1-0042. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government.

Publisher Copyright:
© 2017 IEEE.

Publisher link

10.1109/IEDM.2017.8268521

Find It

Find It at U of M Libraries

Cite this

Kumar, S., Cho, M., Everson, L., Kim, H., Tang, Q., Mazanec, P., Meinerzhagen, P., Malavasi, A., Lake, D., Tokunaga, C., Khellah, M., Tschanz, J., Borkar, S., De, V., & Kim, C. H. (2018). An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits. In 2017 IEEE International Electron Devices Meeting, IEDM 2017 (pp. 39.3.1-39.3.4). (Technical Digest - International Electron Devices Meeting, IEDM). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/IEDM.2017.8268521

An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits. / Kumar, Saurabh; Cho, Minki; Everson, Luke et al.
2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2018. p. 39.3.1-39.3.4 (Technical Digest - International Electron Devices Meeting, IEDM).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Kumar, S, Cho, M, Everson, L, Kim, H, Tang, Q, Mazanec, P, Meinerzhagen, P, Malavasi, A, Lake, D, Tokunaga, C, Khellah, M, Tschanz, J, Borkar, S, De, V & Kim, CH 2018, An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits. in 2017 IEEE International Electron Devices Meeting, IEDM 2017. Technical Digest - International Electron Devices Meeting, IEDM, Institute of Electrical and Electronics Engineers Inc., pp. 39.3.1-39.3.4, 63rd IEEE International Electron Devices Meeting, IEDM 2017, San Francisco, United States, 12/2/17. https://doi.org/10.1109/IEDM.2017.8268521

Kumar S, Cho M, Everson L, Kim H, Tang Q, Mazanec P et al. An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits. In 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc. 2018. p. 39.3.1-39.3.4. (Technical Digest - International Electron Devices Meeting, IEDM). doi: 10.1109/IEDM.2017.8268521

Kumar, Saurabh ; Cho, Minki ; Everson, Luke et al. / An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits. 2017 IEEE International Electron Devices Meeting, IEDM 2017. Institute of Electrical and Electronics Engineers Inc., 2018. pp. 39.3.1-39.3.4 (Technical Digest - International Electron Devices Meeting, IEDM).

@inproceedings{79833b4d5cf14a7ba6ca718bd4ac4d94,

title = "An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits",

abstract = "This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.",

author = "Saurabh Kumar and Minki Cho and Luke Everson and Hoonki Kim and Qianying Tang and Paul Mazanec and Pascal Meinerzhagen and Andres Malavasi and Dan Lake and Carlos Tokunaga and Muhammad Khellah and James Tschanz and Shekhar Borkar and Vivek De and Kim, {Chris H.}",

note = "Funding Information: Acknowledgements: The authors would like to thank Dr. Heather Quinn at Los Alamos National Labs for her help with the neutron beam tests. This work was funded in part by the U.S. Government. The data analysis work was partially supported by the Defense Threat Reduction Agency under Basic Research Award No. HDTRA1-14-1-0042. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government. Publisher Copyright: {\textcopyright} 2017 IEEE.; 63rd IEEE International Electron Devices Meeting, IEDM 2017 ; Conference date: 02-12-2017 Through 06-12-2017",

year = "2018",

month = jan,

day = "23",

doi = "10.1109/IEDM.2017.8268521",

language = "English (US)",

series = "Technical Digest - International Electron Devices Meeting, IEDM",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "39.3.1--39.3.4",

booktitle = "2017 IEEE International Electron Devices Meeting, IEDM 2017",

}

TY - GEN

T1 - An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits

AU - Kumar, Saurabh

AU - Cho, Minki

AU - Everson, Luke

AU - Kim, Hoonki

AU - Tang, Qianying

AU - Mazanec, Paul

AU - Meinerzhagen, Pascal

AU - Malavasi, Andres

AU - Lake, Dan

AU - Tokunaga, Carlos

AU - Khellah, Muhammad

AU - Tschanz, James

AU - Borkar, Shekhar

AU - De, Vivek

AU - Kim, Chris H.

N1 - Funding Information: Acknowledgements: The authors would like to thank Dr. Heather Quinn at Los Alamos National Labs for her help with the neutron beam tests. This work was funded in part by the U.S. Government. The data analysis work was partially supported by the Defense Threat Reduction Agency under Basic Research Award No. HDTRA1-14-1-0042. The views and conclusions contained in this document are those of the authors and should not be interpreted as representing the official policies, either expressed or implied, of the U.S. Government. Publisher Copyright: © 2017 IEEE.

PY - 2018/1/23

Y1 - 2018/1/23

N2 - This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.

AB - This paper describes a 14nm test chip employing a novel NAND/NOR readout chain for characterizing soft error rate (SER) in combinational logic gates. The proposed test structure uses high density standard logic gates as detection circuit for sensing Single Event Transients (SETs) that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.

UR - http://www.scopus.com/inward/record.url?scp=85045200626&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85045200626&partnerID=8YFLogxK

U2 - 10.1109/IEDM.2017.8268521

DO - 10.1109/IEDM.2017.8268521

M3 - Conference contribution

AN - SCOPUS:85045200626

T3 - Technical Digest - International Electron Devices Meeting, IEDM

SP - 39.3.1-39.3.4

BT - 2017 IEEE International Electron Devices Meeting, IEDM 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 63rd IEEE International Electron Devices Meeting, IEDM 2017

Y2 - 2 December 2017 through 6 December 2017

ER -

An ultra-dense irradiation test structure with a NAND/NOR readout chain for characterizing soft error rates of 14nm combinational logic circuits

Abstract

Publication series

Other

Bibliographical note

Publisher link

Find It

Other files and links

Fingerprint

Cite this