Abstract
With the help of assertion based verification, engineers nowadays can check a digital design against its specification more easily and precisely. What's more, assertion descriptions can be synthesized into hardware, which makes post-fab on-line monitor possible. But most of the paper does not consider waveform capture and off-line replay features that can help engineers further analyze captured waveforms. In this paper, an assertion based hardware monitor with off-line replay is presented. Its SAV to RTL generator is described.
Original language | English (US) |
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Title of host publication | 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings |
Editors | Yu-Long Jiang, Ting-Ao Tang, Ru Huang |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 1612-1614 |
Number of pages | 3 |
ISBN (Electronic) | 9781467397179 |
DOIs | |
State | Published - 2016 |
Event | 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Hangzhou, China Duration: Oct 25 2016 → Oct 28 2016 |
Publication series
Name | 2016 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 - Proceedings |
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Other
Other | 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, ICSICT 2016 |
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Country/Territory | China |
City | Hangzhou |
Period | 10/25/16 → 10/28/16 |
Bibliographical note
Funding Information:This paper is supported by the Samsun Electronics Co., Ltd., grant no. SLSI-201509DD003, and by the State Key Lab of ASIC and System, grant No. 2016GF010.
Publisher Copyright:
© 2016 IEEE.
Keywords
- Assertion
- Off-line replay
- On-line Monitor
- SVA Compiler