TY - JOUR
T1 - An SRAM reliability test macro for fully automated statistical measurements of VMIN degradation
AU - Kim, Tony Tae Hyoung
AU - Zhang, Wei
AU - Kim, Chris H.
PY - 2012/3
Y1 - 2012/3
N2 - Negative bias temperature instability (NBTI) has been considered as a main reliability issue in SRAMs since the threshold voltage degradation of PMOS transistors due to NBTI has raised minimum operating voltage (VMIN) over time. This paper explains an SRAM reliability test macro designed in a 1.2 V, 65 nm CMOS process technology for statistical measurements of VMIN degradation coming from NBTI. An automated test program efficiently collects statistical VMIN data and reduces test time. The proposed test structure enables VMIN degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The VMIN dependency on initial device mismatch and stored data is also presented. The measured time to cell data flip affected by NBTI shows the similar trend of NBTI following a power-law dependency on stress time.
AB - Negative bias temperature instability (NBTI) has been considered as a main reliability issue in SRAMs since the threshold voltage degradation of PMOS transistors due to NBTI has raised minimum operating voltage (VMIN) over time. This paper explains an SRAM reliability test macro designed in a 1.2 V, 65 nm CMOS process technology for statistical measurements of VMIN degradation coming from NBTI. An automated test program efficiently collects statistical VMIN data and reduces test time. The proposed test structure enables VMIN degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The VMIN dependency on initial device mismatch and stored data is also presented. The measured time to cell data flip affected by NBTI shows the similar trend of NBTI following a power-law dependency on stress time.
KW - Circuit reliability
KW - Negative bias temperature instability (NBTI)
KW - Static random access memory (SRAM)
UR - http://www.scopus.com/inward/record.url?scp=84899477112&partnerID=8YFLogxK
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U2 - 10.1109/TCSI.2011.2167264
DO - 10.1109/TCSI.2011.2167264
M3 - Article
AN - SCOPUS:84899477112
SN - 1549-8328
VL - 59
SP - 584
EP - 593
JO - IEEE Transactions on Circuits and Systems I: Regular Papers
JF - IEEE Transactions on Circuits and Systems I: Regular Papers
IS - 3
M1 - 2167264
ER -