An SRAM reliability test macro for fully-automated statistical measurements of Vmin degradation

Tae Hyoung Kim, Wei Zhang, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Scopus citations

Abstract

An SRAM reliability test macro is designed in a 1.2V, 65nm CMOS process for statistical measurements of Vmin degradation. An automated test program efficiently collects statistical Vmin data and reduces test time. The proposed test structure enables Vmin degradation measurements for different SRAM failure modes such as the SNM-limited case and the access-time-limited case. The impact of voltage stress on the time to cell data flip was measured.

Original languageEnglish (US)
Title of host publication2009 IEEE Custom Integrated Circuits Conference, CICC '09
Pages231-234
Number of pages4
DOIs
StatePublished - 2009
Event2009 IEEE Custom Integrated Circuits Conference, CICC '09 - San Jose, CA, United States
Duration: Sep 13 2009Sep 16 2009

Publication series

NameProceedings of the Custom Integrated Circuits Conference
ISSN (Print)0886-5930

Other

Other2009 IEEE Custom Integrated Circuits Conference, CICC '09
CountryUnited States
CitySan Jose, CA
Period9/13/099/16/09

Fingerprint Dive into the research topics of 'An SRAM reliability test macro for fully-automated statistical measurements of V<sub>min</sub> degradation'. Together they form a unique fingerprint.

Cite this