An on-chip NBTI sensor for measuring pMOS threshold voltage degradation

John Keane, Tae Hyoung Kim, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

66 Scopus citations


Negative bias temperature instability (NBTI) is one of the most critical device reliability issues in sub-130 nm CMOS processes. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using a delay-locked loop (DLL), in which the increase in pMOS threshold voltage due to NBTI stress is translated into a control voltage shift in the DLL for high sensing gain. The proposed sensor is capable of supporting both DC and AC stress modes. Measurements from a test chip fabricated in a 130 nm bulk CMOS process show an average gain of 10 × in the operating range of interest, with measurement times in tens of microseconds possible for minimal unwanted threshold voltage recovery. NBTI degradation readings across a range of operating conditions are presented to demonstrate the flexibility of this system.

Original languageEnglish (US)
Article number5299235
Pages (from-to)947-956
Number of pages10
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number6
StatePublished - Jun 2010

Bibliographical note

Funding Information:
Manuscript received March 28, 2008; revised July 07, 2008. First published October 30, 2009; current version published May 26, 2010. This work was supported in part by Intel and IBM. The authors are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: jkeane@ece. Digital Object Identifier 10.1109/TVLSI.2009.2017751 Fig. 1. Cross section of a pMOS device under (a) NBTI stress and (b) in recovery mode.

Copyright 2010 Elsevier B.V., All rights reserved.


  • Delay locked loop (DLL)
  • Negative bias temperature instability (NBTI)
  • Reliability


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