An on-chip NBTI sensor for measuring PMOS threshold voltage degradation

John Keane, Tae Hyoung Kim, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

44 Scopus citations

Abstract

Negative Bias Temperature Instability (NBTI) is one of the most critical device reliability issues facing scaled CMOS technology. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using two delay-locked loops (DLL). The increase in PMOS transistor threshold due to NBTI stress is translated into the control voltage of a DLL for high sensing gain. Measurements from a 0.13m test chip show a maximum gain of 16X in the operating range of interest, with microsecond order measurement times for minimal unwanted recovery. The proposed NBTI sensor also supports various DC and AC stress modes.

Original languageEnglish (US)
Title of host publicationISLPED'07
Subtitle of host publicationProceedings of the 2007 International Symposium on Low Power Electronics and Design
Pages189-194
Number of pages6
DOIs
StatePublished - Dec 17 2007
EventISLPED'07: 2007 International Symposium on Low Power Electronics and Design - Portland, OR, United States
Duration: Aug 27 2007Aug 29 2007

Publication series

NameProceedings of the International Symposium on Low Power Electronics and Design
ISSN (Print)1533-4678

Other

OtherISLPED'07: 2007 International Symposium on Low Power Electronics and Design
CountryUnited States
CityPortland, OR
Period8/27/078/29/07

Keywords

  • Aging
  • Delay
  • Locked loop
  • NBTI

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    Keane, J., Kim, T. H., & Kim, C. H. (2007). An on-chip NBTI sensor for measuring PMOS threshold voltage degradation. In ISLPED'07: Proceedings of the 2007 International Symposium on Low Power Electronics and Design (pp. 189-194). (Proceedings of the International Symposium on Low Power Electronics and Design). https://doi.org/10.1145/1283780.1283821