An integrated framework for compiler-directed cache coherence and data prefetching

Hock Beng Lim; Pen Chung Yew

doi:10.1007/3-540-48319-5_4

An integrated framework for compiler-directed cache coherence and data prefetching

Hock Beng Lim
, Pen Chung Yew

Computer Science and Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

Cache coherence enforcement and memory latency reduction and hiding are very important and challenging problems in the design of large-scale distributed shared-memory (DSM) multiprocessors. We pro- pose an integrated approach to solve these problems through a compiler- directed cache coherence scheme called the Cache Coherence with Data Prefetching (CCDP) scheme. The CCDP scheme enforces cache coher- ence by prefetching the potentially-stale references in a parallel program. It also prefetches the non-stale references to hide their memory latencies. To optimize the performance of the CCDP scheme, some prefetch hard- ware support is provided to eficiently handle these two forms of data prefetching operations. We also developed the compiler techniques uti- lized by the CCDP scheme for stale reference detection, prefetch target analysis and prefetch scheduling. We evaluated the performance of the CCDP scheme via execution-driven simulations of several applications from the SPEC CFP95 and CFP92 benchmark suites. The simulation results show that the CCDP scheme provides significant performance improvements for the benchmark programs studied.

Original language	English (US)
Title of host publication	Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings
Editors	Siddhartha Chatterjee, Jan F. Prins, Larry Carter, Jeanne Ferrante, Zhiyuan Li, David Sehr, Pen-Chung Yew
Publisher	Springer Verlag
Pages	51-67
Number of pages	17
ISBN (Print)	3540664262, 9783540664260
DOIs	https://doi.org/10.1007/3-540-48319-5_4
State	Published - 1999
Event	11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998 - Chapel Hill, United States Duration: Aug 7 1998 → Aug 9 1998

Publication series

Name	Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume	1656
ISSN (Print)	0302-9743
ISSN (Electronic)	1611-3349

Other

Other	11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998
Country/Territory	United States
City	Chapel Hill
Period	8/7/98 → 8/9/98

Bibliographical note

Publisher Copyright:
© Springer-Verlag Berlin Heidelberg 1999.

Keywords

Compiler-directed cache coherence
Data prefetching
Memory latency hiding
Shared-memory multiprocessors

Publisher link

10.1007/3-540-48319-5_4

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Lim, H. B., & Yew, P. C. (1999). An integrated framework for compiler-directed cache coherence and data prefetching. In S. Chatterjee, J. F. Prins, L. Carter, J. Ferrante, Z. Li, D. Sehr, & P.-C. Yew (Eds.), Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings (pp. 51-67). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1656). Springer Verlag. https://doi.org/10.1007/3-540-48319-5_4

An integrated framework for compiler-directed cache coherence and data prefetching. / Lim, Hock Beng; Yew, Pen Chung.
Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. ed. / Siddhartha Chatterjee; Jan F. Prins; Larry Carter; Jeanne Ferrante; Zhiyuan Li; David Sehr; Pen-Chung Yew. Springer Verlag, 1999. p. 51-67 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 1656).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Lim, HB & Yew, PC 1999, An integrated framework for compiler-directed cache coherence and data prefetching. in S Chatterjee, JF Prins, L Carter, J Ferrante, Z Li, D Sehr & P-C Yew (eds), Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), vol. 1656, Springer Verlag, pp. 51-67, 11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998, Chapel Hill, United States, 8/7/98. https://doi.org/10.1007/3-540-48319-5_4

Lim HB, Yew PC. An integrated framework for compiler-directed cache coherence and data prefetching. In Chatterjee S, Prins JF, Carter L, Ferrante J, Li Z, Sehr D, Yew PC, editors, Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. Springer Verlag. 1999. p. 51-67. (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)). doi: 10.1007/3-540-48319-5_4

Lim, Hock Beng ; Yew, Pen Chung. / An integrated framework for compiler-directed cache coherence and data prefetching. Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings. editor / Siddhartha Chatterjee ; Jan F. Prins ; Larry Carter ; Jeanne Ferrante ; Zhiyuan Li ; David Sehr ; Pen-Chung Yew. Springer Verlag, 1999. pp. 51-67 (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)).

@inproceedings{1b5f2c2b7cd24f0f9e27ce40a6b57b1d,

title = "An integrated framework for compiler-directed cache coherence and data prefetching",

abstract = "Cache coherence enforcement and memory latency reduction and hiding are very important and challenging problems in the design of large-scale distributed shared-memory (DSM) multiprocessors. We pro- pose an integrated approach to solve these problems through a compiler- directed cache coherence scheme called the Cache Coherence with Data Prefetching (CCDP) scheme. The CCDP scheme enforces cache coher- ence by prefetching the potentially-stale references in a parallel program. It also prefetches the non-stale references to hide their memory latencies. To optimize the performance of the CCDP scheme, some prefetch hard- ware support is provided to eficiently handle these two forms of data prefetching operations. We also developed the compiler techniques uti- lized by the CCDP scheme for stale reference detection, prefetch target analysis and prefetch scheduling. We evaluated the performance of the CCDP scheme via execution-driven simulations of several applications from the SPEC CFP95 and CFP92 benchmark suites. The simulation results show that the CCDP scheme provides significant performance improvements for the benchmark programs studied.",

keywords = "Compiler-directed cache coherence, Data prefetching, Memory latency hiding, Shared-memory multiprocessors",

author = "Lim, \{Hock Beng\} and Yew, \{Pen Chung\}",

note = "Publisher Copyright: {\textcopyright} Springer-Verlag Berlin Heidelberg 1999.; 11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998 ; Conference date: 07-08-1998 Through 09-08-1998",

year = "1999",

doi = "10.1007/3-540-48319-5\_4",

language = "English (US)",

isbn = "3540664262",

series = "Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)",

publisher = "Springer Verlag",

pages = "51--67",

editor = "Siddhartha Chatterjee and Prins, \{Jan F.\} and Larry Carter and Jeanne Ferrante and Zhiyuan Li and David Sehr and Pen-Chung Yew",

booktitle = "Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings",

}

TY - GEN

T1 - An integrated framework for compiler-directed cache coherence and data prefetching

AU - Lim, Hock Beng

AU - Yew, Pen Chung

N1 - Publisher Copyright: © Springer-Verlag Berlin Heidelberg 1999.

PY - 1999

Y1 - 1999

N2 - Cache coherence enforcement and memory latency reduction and hiding are very important and challenging problems in the design of large-scale distributed shared-memory (DSM) multiprocessors. We pro- pose an integrated approach to solve these problems through a compiler- directed cache coherence scheme called the Cache Coherence with Data Prefetching (CCDP) scheme. The CCDP scheme enforces cache coher- ence by prefetching the potentially-stale references in a parallel program. It also prefetches the non-stale references to hide their memory latencies. To optimize the performance of the CCDP scheme, some prefetch hard- ware support is provided to eficiently handle these two forms of data prefetching operations. We also developed the compiler techniques uti- lized by the CCDP scheme for stale reference detection, prefetch target analysis and prefetch scheduling. We evaluated the performance of the CCDP scheme via execution-driven simulations of several applications from the SPEC CFP95 and CFP92 benchmark suites. The simulation results show that the CCDP scheme provides significant performance improvements for the benchmark programs studied.

AB - Cache coherence enforcement and memory latency reduction and hiding are very important and challenging problems in the design of large-scale distributed shared-memory (DSM) multiprocessors. We pro- pose an integrated approach to solve these problems through a compiler- directed cache coherence scheme called the Cache Coherence with Data Prefetching (CCDP) scheme. The CCDP scheme enforces cache coher- ence by prefetching the potentially-stale references in a parallel program. It also prefetches the non-stale references to hide their memory latencies. To optimize the performance of the CCDP scheme, some prefetch hard- ware support is provided to eficiently handle these two forms of data prefetching operations. We also developed the compiler techniques uti- lized by the CCDP scheme for stale reference detection, prefetch target analysis and prefetch scheduling. We evaluated the performance of the CCDP scheme via execution-driven simulations of several applications from the SPEC CFP95 and CFP92 benchmark suites. The simulation results show that the CCDP scheme provides significant performance improvements for the benchmark programs studied.

KW - Compiler-directed cache coherence

KW - Data prefetching

KW - Memory latency hiding

KW - Shared-memory multiprocessors

UR - https://www.scopus.com/pages/publications/84947912720

UR - https://www.scopus.com/pages/publications/84947912720#tab=citedBy

U2 - 10.1007/3-540-48319-5_4

DO - 10.1007/3-540-48319-5_4

M3 - Conference contribution

AN - SCOPUS:84947912720

SN - 3540664262

SN - 9783540664260

T3 - Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)

SP - 51

EP - 67

BT - Languages and Compilers for Parallel Computing - 11th International Workshop, LCPC 1998, Proceedings

A2 - Chatterjee, Siddhartha

A2 - Prins, Jan F.

A2 - Carter, Larry

A2 - Ferrante, Jeanne

A2 - Li, Zhiyuan

A2 - Sehr, David

A2 - Yew, Pen-Chung

PB - Springer Verlag

T2 - 11th International Workshop on Languages and Compilers for Parallel Computing, LCPC 1998

Y2 - 7 August 1998 through 9 August 1998

ER -

An integrated framework for compiler-directed cache coherence and data prefetching

Abstract

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Keywords

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