An in-place fft architecture for real-valued signals

Manohar Ayinala, Yingjie Lao, Keshab K Parhi

Research output: Contribution to journalArticle

38 Citations (Scopus)

Abstract

This brief presents a novel scalable architecture for in-place fast Fourier transform (IFFT) computation for real-valued signals. The proposed computation is based on a modified radix-2 algorithm, which removes the redundant operations from the flow graph. A new processing element (PE) is proposed using two radix-2 butterflies that can process four inputs in parallel. A novel conflict-free memory-addressing scheme is proposed to ensure the continuous operation of the FFT processor. Furthermore, the addressing scheme is extended to support multiple parallel PEs. The proposed real-FFT processor simultaneously requires fewer computation cycles and lower hardware cost compared to prior work. For example, the proposed design with two PEs reduces the computation cycles by a factor of 2 for a 256-point real fast Fourier transform (RFFT) compared to a prior work while maintaining a lower hardware complexity. The number of computation cycles is reduced proportionately with the increase in the number of PEs.

Original languageEnglish (US)
Article number6576819
Pages (from-to)652-656
Number of pages5
JournalIEEE Transactions on Circuits and Systems II: Express Briefs
Volume60
Issue number10
DOIs
StatePublished - Aug 19 2013

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Fast Fourier transforms
Hardware
Flow graphs
Data storage equipment
Processing
Costs

Keywords

  • Continuous flow
  • fast Fourier transform (FFT)
  • Hermitian symmetric
  • in-place
  • memory-addressing scheme
  • real fast Fourier transform (RFFT)
  • real in-place fast Fourier transform (RIFFT)

Cite this

An in-place fft architecture for real-valued signals. / Ayinala, Manohar; Lao, Yingjie; Parhi, Keshab K.

In: IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 60, No. 10, 6576819, 19.08.2013, p. 652-656.

Research output: Contribution to journalArticle

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