An FPGA implementation of a Restricted Boltzmann Machine classifier using stochastic bit streams

Bingzhe Li, M. Hassan Najafi, David J. Lilja

Research output: Chapter in Book/Report/Conference proceedingConference contribution

19 Scopus citations

Abstract

Artificial neural networks (ANNs) usually require a very large number of computation nodes and can be implemented either in software or directly in hardware, such as FPGAs. Software-based approaches are offline and not suitable for real-time applications, but they support a large number of nodes. FPGA-based implementations, in contrast, can greatly speedup the computation time. However, resource limitations in an FPGA restrict the maximum number of computation nodes in hardware-based approaches. This work exploits stochastic bit streams to implement the Restricted Boltzmann Machine (RBM) handwritten digit recognition application completely on an FPGA. Exploiting this approach saves a large number of hardware resources making the FPGA-based implementation of large ANNs feasible.

Original languageEnglish (US)
Title of host publicationProceedings of the ASAP 2015 - 2015 IEEE 26th International Conference on Application-Specific Systems, Architectures and Processors
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages68-69
Number of pages2
ISBN (Electronic)9781479919246
DOIs
StatePublished - Sep 8 2015
Event26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015 - Toronto, Canada
Duration: Jul 27 2015Jul 29 2015

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2015-September
ISSN (Print)1063-6862

Other

Other26th IEEE International Conference on Application-Specific Systems, Architectures and Processors, ASAP 2015
CountryCanada
CityToronto
Period7/27/157/29/15

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