A general sequential circuit consists of a number of combinational stages that lie between latches. For the circuit to meet a given clocking specification, it is necessary for each combinational stage to satisfy a certain delay requirement. Roughly speaking, increasing the sizes of some transistors in a stage reduces the delay, with the penalty of increased area. The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given specification. Although this problem has been recognized as a convex programming problem, most existing approaches do not take full advantage of this fact, and often give nonoptimal results. An efficient convex optimization algorithm has been used here. This algorithm is guaranteed to find the exact solution to the convex programming problem. We have also improved upon existing methods for computing the circuit delay as an Elmore time constant, to achieve higher accuracy. CMOS circuit examples, including a combinational circuit with 832 transistors are presented to demonstrate the efficacy of the new algorithm.
|Original language||English (US)|
|Number of pages||14|
|Journal||IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems|
|State||Published - Nov 1993|
Bibliographical noteFunding Information:
Manuscript received January 8, 1993. This work was supported in part by the Joint Services Electronics Program under Contract N00014-90-J-1270, the Illinois Technology Challenge Grant under Contract SCCA-92-82122, and the National Science Foundation under Contracts CCR-9057-481 and CCR-9007-195. This paper was recommended by Associate Editor R. Bryant.