An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm

Luke R. Everson, Muqing Liu, Nakul Pande, Chris H. Kim

Research output: Contribution to journalArticle

Abstract

As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65-nm LP CMOS, we achieve an energy efficiency of 104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC.

Original languageEnglish (US)
Article number8718342
Pages (from-to)2777-2785
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume54
Issue number10
DOIs
StatePublished - Oct 1 2019

Fingerprint

Static random access storage
Error correction
Particle accelerators
Energy efficiency
Neural networks
Processing

Keywords

  • Machine learning (ML)
  • neuromorphic computing
  • time-domain computing
  • time-to-digital converter (TDC)

Cite this

An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm. / Everson, Luke R.; Liu, Muqing; Pande, Nakul; Kim, Chris H.

In: IEEE Journal of Solid-State Circuits, Vol. 54, No. 10, 8718342, 01.10.2019, p. 2777-2785.

Research output: Contribution to journalArticle

@article{32bd97b1bc7e426e85e705fc8673eecd,
title = "An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm",
abstract = "As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65-nm LP CMOS, we achieve an energy efficiency of 104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC.",
keywords = "Machine learning (ML), neuromorphic computing, time-domain computing, time-to-digital converter (TDC)",
author = "Everson, {Luke R.} and Muqing Liu and Nakul Pande and Kim, {Chris H.}",
year = "2019",
month = "10",
day = "1",
doi = "10.1109/JSSC.2019.2914361",
language = "English (US)",
volume = "54",
pages = "2777--2785",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "10",

}

TY - JOUR

T1 - An Energy-Efficient One-Shot Time-Based Neural Network Accelerator Employing Dynamic Threshold Error Correction in 65 nm

AU - Everson, Luke R.

AU - Liu, Muqing

AU - Pande, Nakul

AU - Kim, Chris H.

PY - 2019/10/1

Y1 - 2019/10/1

N2 - As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65-nm LP CMOS, we achieve an energy efficiency of 104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC.

AB - As neural networks continue to infiltrate diverse application domains, computing will begin to move out of the cloud and onto edge devices necessitating fast, reliable, and low-power (LP) solutions. To meet these requirements, we propose a time-domain core using one-shot delay measurements and a lightweight post-processing technique, dynamic threshold error correction (DTEC). This design differs from traditional digital implementations in that it uses the delay accumulated through a simple inverter chain distributed through an SRAM array to intrinsically compute resource intensive multiply-accumulate (MAC) operations. Implemented in 65-nm LP CMOS, we achieve an energy efficiency of 104.8 TOp/s/W at 0.7-V with 3b resolution for 19.1 fJ/MAC.

KW - Machine learning (ML)

KW - neuromorphic computing

KW - time-domain computing

KW - time-to-digital converter (TDC)

UR - http://www.scopus.com/inward/record.url?scp=85072777898&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85072777898&partnerID=8YFLogxK

U2 - 10.1109/JSSC.2019.2914361

DO - 10.1109/JSSC.2019.2914361

M3 - Article

AN - SCOPUS:85072777898

VL - 54

SP - 2777

EP - 2785

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 10

M1 - 8718342

ER -