An Embedded nand Flash-Based Compute-In-Memory Array Demonstrated in a Standard Logic Process

Minsu Kim, Muqing Liu, Luke R. Everson, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

2 Scopus citations

Abstract

A neural network hardware inspired by the 3-D NAND flash array structure was experimentally demonstrated in a standard 65-nm CMOS process. Logic-compatible embedded flash memory cells were used for storing multi-level synaptic weights while a bit-serial architecture enables 8 bit × 8 bit multiply-and-accumulate operation. A novel back-pattern tolerant program-verify scheme reduces the cell current variation to less than 0.6 μA. Positive and negative weights are stored in adjacent bitlines, generating a differential output signal. Our eNAND-based neural network core achieves a 98.5% handwritten digit recognition accuracy which is within 0.5% of the software accuracy for the same weight precision. To the best of our knowledge, this work represents the first physical demonstration of an embedded NAND flash-based compute-in-memory chip in a standard logic process.

Original languageEnglish (US)
Pages (from-to)625-638
Number of pages14
JournalIEEE Journal of Solid-State Circuits
Volume57
Issue number2
DOIs
StatePublished - Jan 1 2021

Bibliographical note

Publisher Copyright:
IEEE

Keywords

  • Arrays
  • Common Information Model (computing)
  • Computer architecture
  • Manganese
  • Nonvolatile memory
  • Programmable logic arrays
  • Standards

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