An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS

We present a fully integrated hybrid filter bank ADC based on an analog-FFT geared for baseband signal processing in wireless receivers. The design consists of an 8-point A-FFT for an analysis filter bank, a VGA bank and a sub-ADC bank in the analog domain, and an inverse VGA bank, calibration and inverse FFT for the synthesis filter in the digital domain. The proposed structure enables the signals in each channel of the 450MHz wide band system to be separately digitized using the full dynamic range of the ADC. The prototype is implemented in TSMC's 40nm CMOS GP process. A hybrid filter bank ADC does not have a constant average noise floor and is best used when both large and small signals are present. After calibration, the reconstructed signal with an asymmetric (40dB difference) two tone input, i.e., one large at 1MHz and one small at 225.05MHz shows 55.7dB of image rejection. The SNDR of the smaller signal improves by 6.0dB in comparison to a non-channelized ADC. The total power consumption for both the analog and digital sections is 90.4mW. As far as we are aware this is the first integrated implementation of the full hybrid filter bank principle.