An efficient technology mapping algorithm targeting routing congestion under delay constraints

Rupesh S. Shelar, Xinning Wang, Prashant Saxena, Sachin S. Sapatnekar

Research output: Contribution to conferencePaper

9 Scopus citations

Abstract

Routing congestion has become a serious concern in today's VLSI designs. In this paper, we propose a technology mapping algorithm that minimizes routing congestion under delay constraints. The algorithm employs a dynamic programming framework in the matching phase to generate probabilistic congestion maps for all the matches. These congestion maps are then utilized to minimize routing congestion during the covering, which preserves the delay-optimality of the solution using the notion of slack. Experimental results on benchmark circuits in a 100 nm technology show that the algorithm can improve track overflows by 44%, on an average, as compared to the conventional technology mapping while satisfying delay constraints.

Original languageEnglish (US)
Pages137-144
Number of pages8
DOIs
StatePublished - 2005
Event2005 International Symposium on Physical Design, ISPD'05 - San Francisco, CA, United States
Duration: Apr 3 2005Apr 6 2005

Other

Other2005 International Symposium on Physical Design, ISPD'05
CountryUnited States
CitySan Francisco, CA
Period4/3/054/6/05

Keywords

  • Logic synthesis
  • Routing congestion
  • Technology mapping

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    Shelar, R. S., Wang, X., Saxena, P., & Sapatnekar, S. S. (2005). An efficient technology mapping algorithm targeting routing congestion under delay constraints. 137-144. Paper presented at 2005 International Symposium on Physical Design, ISPD'05, San Francisco, CA, United States. https://doi.org/10.1145/1055137.1055166