An efficient pipelined FFT architecture

Yun Nan Chang; Keshab K. Parhi

doi:10.1109/TCSII.2003.811439

An efficient pipelined FFT architecture

Yun Nan Chang, Keshab K. Parhi

Electrical and Computer Engineering

Research output: Contribution to journal › Article › peer-review

67 Scopus citations

Abstract

This paper presents an efficient VLSI architecture of the pipeline fast Fourier transform (FFT) processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By combining both the feedforward and feedback commutator schemes, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

Original language	English (US)
Pages (from-to)	322-325
Number of pages	4
Journal	IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume	50
Issue number	6
DOIs	https://doi.org/10.1109/TCSII.2003.811439
State	Published - Jun 2003

Keywords

Digit-serial
Fast Fourier transform (FFT)
Pipelined FFT
Radix-4 FFT

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10.1109/TCSII.2003.811439

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abstract = "This paper presents an efficient VLSI architecture of the pipeline fast Fourier transform (FFT) processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By combining both the feedforward and feedback commutator schemes, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.",

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AB - This paper presents an efficient VLSI architecture of the pipeline fast Fourier transform (FFT) processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By combining both the feedforward and feedback commutator schemes, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

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KW - Pipelined FFT

KW - Radix-4 FFT

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An efficient pipelined FFT architecture

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