An efficient pipelined FFT architecture

Yun Nan Chang, Keshab K. Parhi

Research output: Contribution to journalArticlepeer-review

65 Scopus citations

Abstract

This paper presents an efficient VLSI architecture of the pipeline fast Fourier transform (FFT) processor based on radix-4 decimation-in-time algorithm with the use of digit-serial arithmetic units. By combining both the feedforward and feedback commutator schemes, the proposed architecture can not only achieve nearly 100% hardware utilization, but also require much less memory compared with the previous digit-serial FFT processors. Furthermore, in FFT processors, several modules of ROM are required for the storage of twiddle factors. By exploiting the redundancy of the factors, the overall ROM size can be effectively reduced by a factor of 2.

Original languageEnglish (US)
Pages (from-to)322-325
Number of pages4
JournalIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing
Volume50
Issue number6
DOIs
StatePublished - Jun 2003

Bibliographical note

Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.

Keywords

  • Digit-serial
  • Fast Fourier transform (FFT)
  • Pipelined FFT
  • Radix-4 FFT

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