TY - GEN
T1 - An efficient algorithm for low power pass transistor logic synthesis
AU - Shelar, R. S.
AU - Sapatnekar, Sachin S
PY - 2002/1/1
Y1 - 2002/1/1
N2 - In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power reduction in PTL circuits to that of BDD decomposition and solve the latter using the max-flow min-cut technique. We use transistor level power estimates to guide the BDD decomposition algorithm. We present the results obtained by running our algorithm on a set of MCNC benchmark circuits, and show on an average of 47% power reduction over these circuits; the comparison with the previously proposed low power pass transistor logic synthesis algorithms shows an average improvement of over 23% over the best previously published approach.
AB - In this paper, we address the problem of power dissipation minimization in combinational circuits implemented using pass transistor logic (PTL). We transform the problem of power reduction in PTL circuits to that of BDD decomposition and solve the latter using the max-flow min-cut technique. We use transistor level power estimates to guide the BDD decomposition algorithm. We present the results obtained by running our algorithm on a set of MCNC benchmark circuits, and show on an average of 47% power reduction over these circuits; the comparison with the previously proposed low power pass transistor logic synthesis algorithms shows an average improvement of over 23% over the best previously published approach.
UR - http://www.scopus.com/inward/record.url?scp=34547369344&partnerID=8YFLogxK
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U2 - 10.1109/ASPDAC.2002.994890
DO - 10.1109/ASPDAC.2002.994890
M3 - Conference contribution
AN - SCOPUS:34547369344
T3 - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
SP - 87
EP - 92
BT - Proceedings - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 7th Asia and South Pacific Design Automation Conference, 15th International Conference on VLSI Design, ASP-DAC/VLSI Design 2002
Y2 - 7 January 2002 through 11 January 2002
ER -