An efficient 21.56GBPS AES implementation on FPGA

Keyphrases

• Advanced Encryption Standard Algorithm 100%
• Implementation on FPGA 100%
• Advanced Encryption Standard 100%
• Proposed Design 50%
• Hardware Implementation 50%
• FPGA Implementation 50%
• Proposed Architecture 50%
• Combinational Logic 50%
• GF-2 50%
• Xilinx 50%
• High-performance Architecture 50%
• Key Expansion 50%
• Composite Field Arithmetic 50%
• SubBytes 50%
• Encryptor 50%
• Non-feedback 50%
• Area Requirement 50%
• Sub-pipelining 50%
• Byte 50%
• Feedback Types 50%

Computer Science

• Advanced Encryption Standard Algorithm 100%
• Field Programmable Gate Arrays 100%
• Advanced Encryption Standard 100%
• Pipelining 50%
• Hardware Implementation 50%
• Combinational Logic 50%
• Direct Consequence 50%

Engineering

• Field Programmable Gate Arrays 100%
• Cryptography 100%