This paper presents novel high-speed architectures for the hardware implementation of the Advanced Encryption Standard (AES) algorithm. Unlike previous works which rely on look-up tables to implement the SubBytes and InvSub-Bytes transformations of the AES algorithm, the proposed design employs combinational logic only. As a direct consequence, the unbreakable delay incurred by look-up tables in the conventional approaches is eliminated, and the advantage of sub-pipelining can be further explored. Furthermore, composite field arithmetic is employed to reduce the area requirements, and different implementations for the inversion in subfield GF(2 4) are compared. In addition, an efficient key expansion architecture suitable for the sub-pipelined round units is also presented. Using the proposed architecture, a fully sub-pipelined encryptor with 7 sub-stages in each round unit can achieve a throughput of 21.56Gbps on a Xilinx XCV1000e-8bg560 device in non-feedback modes, which is faster and is 79% more efficient than the fastest previous FPGA implementation known to date.
|Original language||English (US)|
|Number of pages||6|
|Journal||Conference Record - Asilomar Conference on Signals, Systems and Computers|
|State||Published - Dec 1 2004|
|Event||Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers - Pacific Grove, CA, United States|
Duration: Nov 7 2004 → Nov 10 2004