Abstract
In this paper, we present an effective path-oriented timing driven placement algorithm for macro cells. Our constructive algorithm minimizes the longest path in the circuit such that total wire length of the placc- ment does not exceed a bound provided by the user. The algorithm also allows fixed and movable I/O pin- s. It uses the concept of partial paths to reduce the run time and dynamic path delay estimation to update and approximate path delays. Our approach is superior to Lin(l] in terms of quality of solutions and run times.
Original language | English (US) |
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Title of host publication | Proceedings - VLSI Design 1992 |
Subtitle of host publication | The 5th International Conference on VLSI Design, ICVD 1992 |
Publisher | IEEE Computer Society |
Pages | 31-36 |
Number of pages | 6 |
ISBN (Electronic) | 0818624655 |
DOIs | |
State | Published - 1992 |
Event | 5th International Conference on VLSI Design, ICVD 1992 - Banglore, India Duration: Jan 4 1992 → Jan 7 1992 |
Publication series
Name | Proceedings of the IEEE International Conference on VLSI Design |
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ISSN (Print) | 1063-9667 |
Conference
Conference | 5th International Conference on VLSI Design, ICVD 1992 |
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Country/Territory | India |
City | Banglore |
Period | 1/4/92 → 1/7/92 |
Bibliographical note
Publisher Copyright:© 1991 IEEE.