This paper presents a bi-static integrated pulse radar in the E-band based on a digitally modulated transmitter and an analog processing receiver module. The proposed frontend correlator operates at 1Gbps and uses a 1.5-bit sampler to compress the sensing data, enabling a low-speed and energy-efficient digital backend while delivering a high range resolution. The TSMC 65nm chip prototype has a 1.5mm x 1.3mm area and consumes a total of 407mW with only 38mW corresponding to the analog baseband and digital backend. Over-the-air measurements at the 66GHz carrier frequency indicate the measured distance from the correlator output has an RMS error of 11.6cm and the integral non-linearity is less than 10cm across the entire target range, demonstrating the state-of-the-art range resolution with superior energy efficiency.
|Original language||English (US)|
|Title of host publication||2022 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||4|
|State||Published - 2022|
|Event||2022 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2022 - Denver, United States|
Duration: Jun 19 2022 → Jun 21 2022
|Name||2022 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)|
|Conference||2022 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2022|
|Period||6/19/22 → 6/21/22|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work is funded by the DARPA Yound Faculty Award.
© 2022 IEEE.
- analog signal processing
- pulse radar