An array-based test circuit for fully automated gate dielectric breakdown characterization

John Keane; Shrinivas Venkatraman; Paulo Butzen; Chris H. Kim

doi:10.1109/CICC.2008.4672036

An array-based test circuit for fully automated gate dielectric breakdown characterization

John Keane
, Shrinivas Venkatraman
, Paulo Butzen
, Chris H. Kim

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

17 Scopus citations

Abstract

We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.

Original language	English (US)
Article number	4672036
Pages (from-to)	121-124
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672036
State	Published - 2008
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: Sep 21 2008 → Sep 24 2008

Publisher link

10.1109/CICC.2008.4672036

Find It

Find It at U of M Libraries

Cite this

@article{d438266b144b42d3bc13f9e9ff1e266d,

title = "An array-based test circuit for fully automated gate dielectric breakdown characterization",

abstract = "We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.",

author = "John Keane and Shrinivas Venkatraman and Paulo Butzen and Kim, \{Chris H.\}",

year = "2008",

doi = "10.1109/CICC.2008.4672036",

language = "English (US)",

pages = "121--124",

journal = "Proceedings of the Custom Integrated Circuits Conference",

issn = "0886-5930",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 ; Conference date: 21-09-2008 Through 24-09-2008",

}

TY - JOUR

T1 - An array-based test circuit for fully automated gate dielectric breakdown characterization

AU - Keane, John

AU - Venkatraman, Shrinivas

AU - Butzen, Paulo

AU - Kim, Chris H.

PY - 2008

Y1 - 2008

N2 - We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.

AB - We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.

UR - https://www.scopus.com/pages/publications/57849161523

UR - https://www.scopus.com/pages/publications/57849161523#tab=citedBy

U2 - 10.1109/CICC.2008.4672036

DO - 10.1109/CICC.2008.4672036

M3 - Conference article

AN - SCOPUS:57849161523

SN - 0886-5930

SP - 121

EP - 124

JO - Proceedings of the Custom Integrated Circuits Conference

JF - Proceedings of the Custom Integrated Circuits Conference

M1 - 4672036

T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008

Y2 - 21 September 2008 through 24 September 2008

ER -

An array-based test circuit for fully automated gate dielectric breakdown characterization

Abstract

Publisher link

Find It

Other files and links

Fingerprint

Cite this