We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Dec 26 2008|
|Event||IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States|
Duration: Sep 21 2008 → Sep 24 2008