TY - JOUR
T1 - An array-based test circuit for fully automated gate dielectric breakdown characterization
AU - Keane, John
AU - Venkatraman, Shrinivas
AU - Butzen, Paulo
AU - Kim, Chris H.
PY - 2008
Y1 - 2008
N2 - We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.
AB - We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.
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U2 - 10.1109/CICC.2008.4672036
DO - 10.1109/CICC.2008.4672036
M3 - Conference article
AN - SCOPUS:57849161523
SN - 0886-5930
SP - 121
EP - 124
JO - Proceedings of the Custom Integrated Circuits Conference
JF - Proceedings of the Custom Integrated Circuits Conference
M1 - 4672036
T2 - IEEE 2008 Custom Integrated Circuits Conference, CICC 2008
Y2 - 21 September 2008 through 24 September 2008
ER -