An array-based test circuit for fully automated gate dielectric breakdown characterization

John Keane, Shrinivas Venkatraman, Paulo Butzen, Chris H. Kim

Research output: Contribution to journalConference articlepeer-review

16 Scopus citations

Abstract

We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32times;32 test array implemented in a 130nm process.

Original languageEnglish (US)
Article number4672036
Pages (from-to)121-124
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - Dec 26 2008
EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
Duration: Sep 21 2008Sep 24 2008

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