We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown Weibull distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 × 32 test array implemented in a 130-nm bulk CMOS process. Results show that this system is capable of taking accurate measurements across a range of voltages and temperatures, which is critical for extrapolating accelerated stress experiment results to expected device lifetimes under realistic operating conditions.
|Original language||English (US)|
|Number of pages||9|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - May 2011|
Bibliographical noteFunding Information:
Manuscript received August 29, 2009; revised December 14, 2009. First published February 22, 2010; current version published April 27, 2011. This work was supported in part by the SRC under Award 2008-HJ-1805, along with Sam-sung, Intel, IBM, TI, and UMC.
- circuit reliability
- dielectric breakdown
- digital measurements