An array-based test circuit for fully automated gate dielectric breakdown characterization

John Keane, Shrinivas Venkatraman, Paulo Butzen, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

6 Scopus citations


We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown Weibull distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 × 32 test array implemented in a 130-nm bulk CMOS process. Results show that this system is capable of taking accurate measurements across a range of voltages and temperatures, which is critical for extrapolating accelerated stress experiment results to expected device lifetimes under realistic operating conditions.

Original languageEnglish (US)
Article number5418862
Pages (from-to)787-795
Number of pages9
JournalIEEE Transactions on Very Large Scale Integration (VLSI) Systems
Issue number5
StatePublished - May 2011

Bibliographical note

Funding Information:
Manuscript received August 29, 2009; revised December 14, 2009. First published February 22, 2010; current version published April 27, 2011. This work was supported in part by the SRC under Award 2008-HJ-1805, along with Sam-sung, Intel, IBM, TI, and UMC.


  • Aging
  • circuit reliability
  • dielectric breakdown
  • digital measurements


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