TY - JOUR
T1 - An array-based test circuit for fully automated gate dielectric breakdown characterization
AU - Keane, John
AU - Venkatraman, Shrinivas
AU - Butzen, Paulo
AU - Kim, Chris H.
PY - 2011/5/1
Y1 - 2011/5/1
N2 - We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown Weibull distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 × 32 test array implemented in a 130-nm bulk CMOS process. Results show that this system is capable of taking accurate measurements across a range of voltages and temperatures, which is critical for extrapolating accelerated stress experiment results to expected device lifetimes under realistic operating conditions.
AB - We propose an array-based test circuit for efficiently characterizing gate dielectric breakdown. Such a design is highly beneficial when studying this statistical process, where up to thousands of samples are needed to create an accurate time to breakdown Weibull distribution. The proposed circuit also facilitates investigations of any spatial correlation of dielectric failures, and can monitor a progressive decrease in gate resistance. Measurement results are presented from a 32 × 32 test array implemented in a 130-nm bulk CMOS process. Results show that this system is capable of taking accurate measurements across a range of voltages and temperatures, which is critical for extrapolating accelerated stress experiment results to expected device lifetimes under realistic operating conditions.
KW - Aging
KW - circuit reliability
KW - dielectric breakdown
KW - digital measurements
UR - http://www.scopus.com/inward/record.url?scp=79955561254&partnerID=8YFLogxK
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U2 - 10.1109/TVLSI.2010.2041258
DO - 10.1109/TVLSI.2010.2041258
M3 - Article
AN - SCOPUS:79955561254
VL - 19
SP - 787
EP - 795
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 5
M1 - 5418862
ER -