An array-based circuit for characterizing latent Plasma-Induced Damage

Won Ho Choi, Pulkit Jain, Chris H. Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Scopus citations

Abstract

An array-based Plasma-Induced Damage (PID) characterization circuit with various antenna structures is proposed for efficient collection of massive PID breakdown statistics. The proposed circuit reduces the stress time and test area by a factor proportional to the number of Devices Under Test (DUTs). Measured Weibull statistics from a 12-24 array implemented in 65nm show that DUTs with plate type antennas have a shorter lifetime compared to their fork type counterparts suggesting greater PID effect during the plasma ashing process.

Original languageEnglish (US)
Title of host publication2013 IEEE International Reliability Physics Symposium, IRPS 2013
DOIs
StatePublished - Aug 7 2013
Event2013 IEEE International Reliability Physics Symposium, IRPS 2013 - Monterey, CA, United States
Duration: Apr 14 2013Apr 18 2013

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
ISSN (Print)1541-7026

Other

Other2013 IEEE International Reliability Physics Symposium, IRPS 2013
CountryUnited States
CityMonterey, CA
Period4/14/134/18/13

Keywords

  • Aging
  • Plasma-induced damage
  • Time dependent dielectric breakdown
  • degradation

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  • Cite this

    Choi, W. H., Jain, P., & Kim, C. H. (2013). An array-based circuit for characterizing latent Plasma-Induced Damage. In 2013 IEEE International Reliability Physics Symposium, IRPS 2013 [6532005] (IEEE International Reliability Physics Symposium Proceedings). https://doi.org/10.1109/IRPS.2013.6532005