TY - GEN
T1 - An array-based Chip Lifetime Predictor macro for gate dielectric failures in core and IO FETs
AU - Jain, Pulkit
AU - Keane, John
AU - Kim, Chris H.
PY - 2012/12/11
Y1 - 2012/12/11
N2 - A comprehensive Chip LIfetime Predictor (CLIP) macro for automatically characterizing gate dielectric failure reduces the stress time and silicon area by a factor proportional to the number of FETs to be tested. A flexible DUT cell that can be stressed in isolation without thicker tox FETs to 4 times supply voltage, enables accurate lifetime prediction under different ON and OFF state dielectric breakdown modes for both low voltage core and high voltage IO devices.
AB - A comprehensive Chip LIfetime Predictor (CLIP) macro for automatically characterizing gate dielectric failure reduces the stress time and silicon area by a factor proportional to the number of FETs to be tested. A flexible DUT cell that can be stressed in isolation without thicker tox FETs to 4 times supply voltage, enables accurate lifetime prediction under different ON and OFF state dielectric breakdown modes for both low voltage core and high voltage IO devices.
UR - http://www.scopus.com/inward/record.url?scp=84870579528&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84870579528&partnerID=8YFLogxK
U2 - 10.1109/ESSDERC.2012.6343383
DO - 10.1109/ESSDERC.2012.6343383
M3 - Conference contribution
AN - SCOPUS:84870579528
SN - 9781467317078
T3 - European Solid-State Device Research Conference
SP - 262
EP - 265
BT - 2012 Proceedings of the European Solid-State Device Research Conference, ESSDERC 2012
T2 - 42nd European Solid-State Device Research Conference, ESSDERC 2012
Y2 - 17 September 2012 through 21 September 2012
ER -