Mounting concerns over variability, defects, and noise motivate a new approach for digital circuitry: stochastic logic, that is to say, logic that operates on probabilistic signals and so can cope with errors and uncertainty. Techniques for probabilistic analysis of circuits and systems are well established. We advocate a strategy for synthesis. In prior work, we described a methodology for synthesizing stochastic logic, that is to say logic that operates on probabilistic bit streams. In this paper, we apply the concept of stochastic logic to a reconfigurable architecture that implements processing operations on a datapath. We analyze cost as well as the sources of error: approximation, quantization, and random fluctuations. We study the effectiveness of the architecture on a collection of benchmarks for image processing. The stochastic architecture requires less area than conventional hardware implementations. Moreover, it is much more tolerant of soft errors (bit flips) than these deterministic implementations. This fault tolerance scales gracefully to very large numbers of errors.
Bibliographical noteFunding Information:
This work is supported by a grant from the Semiconductor Research Corporation’s Focus Center Research Program on Functional Engineered Nano-Architectonics, contract No. 2003-NT-1107, a CAREER Award, #0845650, from the US National Science Foundation (NSF), and a grant from Intel Corporation.
- Stochastic logic
- fault-tolerant computation
- reconfigurable hardware