Abstract
Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there exists only a few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate circuits consisting of adders and multipliers, which are the key hardware components used in error-resilient applications. A novel algorithm has been presented, using the Fourier and the Mellin transforms, that efficiently determines the probability distribution of the error introduced by approximation in a circuit, abstracted as a directed acyclic graph. The algorithm is generalized for signed operations through two's complement representation, and its accuracy is demonstrated to be within 1% of Monte Carlo simulations, while being over an order of magnitude faster.
| Original language | English (US) |
|---|---|
| Article number | 8283743 |
| Pages (from-to) | 70-83 |
| Number of pages | 14 |
| Journal | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
| Volume | 38 |
| Issue number | 1 |
| DOIs | |
| State | Published - Jan 1 2019 |
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Keywords
- Approximate computing
- Fourier transform
- Mellin transform
- error distribution
Cite this
An analytical approach for error PMF characterization in approximate circuits. / Sengupta, Deepashree; Snigdha, Farhana Sharmin; Hu, Jiang; Sapatnekar, Sachin S.
In: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 38, No. 1, 8283743, 01.01.2019, p. 70-83.Research output: Contribution to journal › Article
}
TY - JOUR
T1 - An analytical approach for error PMF characterization in approximate circuits
AU - Sengupta, Deepashree
AU - Snigdha, Farhana Sharmin
AU - Hu, Jiang
AU - Sapatnekar, Sachin S
PY - 2019/1/1
Y1 - 2019/1/1
N2 - Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there exists only a few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate circuits consisting of adders and multipliers, which are the key hardware components used in error-resilient applications. A novel algorithm has been presented, using the Fourier and the Mellin transforms, that efficiently determines the probability distribution of the error introduced by approximation in a circuit, abstracted as a directed acyclic graph. The algorithm is generalized for signed operations through two's complement representation, and its accuracy is demonstrated to be within 1% of Monte Carlo simulations, while being over an order of magnitude faster.
AB - Approximate computing has emerged as a circuit design technique that can reduce system power without significantly sacrificing the output quality in error-resilient applications. However, there exists only a few approaches for systematically and efficiently determining the error introduced by approximate hardware units. This paper focuses on the development of error analysis techniques for approximate circuits consisting of adders and multipliers, which are the key hardware components used in error-resilient applications. A novel algorithm has been presented, using the Fourier and the Mellin transforms, that efficiently determines the probability distribution of the error introduced by approximation in a circuit, abstracted as a directed acyclic graph. The algorithm is generalized for signed operations through two's complement representation, and its accuracy is demonstrated to be within 1% of Monte Carlo simulations, while being over an order of magnitude faster.
KW - Approximate computing
KW - Fourier transform
KW - Mellin transform
KW - error distribution
UR - http://www.scopus.com/inward/record.url?scp=85041519500&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85041519500&partnerID=8YFLogxK
U2 - 10.1109/TCAD.2018.2803626
DO - 10.1109/TCAD.2018.2803626
M3 - Article
AN - SCOPUS:85041519500
VL - 38
SP - 70
EP - 83
JO - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JF - IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SN - 0278-0070
IS - 1
M1 - 8283743
ER -