An all-in-one silicon odometer for separately monitoring HCI, BTI, and TDDB

John Keane, Xiaofei Wang, Devin Persaud, Chris H. Kim

Research output: Contribution to journalArticlepeer-review

139 Scopus citations


We present an on-chip reliability monitor capable of separating the aging effects of hot carrier injection (HCI), bias temperature instability (BTI), and time-dependent dielectric breakdown (TDDB) with high frequency resolution. This task is accomplished with a pair of modified ring oscillators (ROSCs) which are representative of standard CMOS circuits. We use a backdrive concept, in which one ROSC drives the voltage transitions in both structures during stress, such that the driving oscillator ages due to both BTI and HCI, while the other suffers from only BTI. In addition, long term or high voltage experiments facilitate TDDB measurements in both oscillators. Sub-μs measurements are controlled by on-chip logic in order to avoid excessive unwanted BTI recovery during stress interruptions. Sub-ps frequency resolution is achieved during these short measurements using a beat frequency detection system, and we automate the experiments through a simple digital interface. Measurement results are presented from a 65 nm test chip over a range of stress conditions.

Original languageEnglish (US)
Article number5437493
Pages (from-to)817-829
Number of pages13
JournalIEEE Journal of Solid-State Circuits
Issue number4
StatePublished - Apr 2010

Bibliographical note

Funding Information:
Manuscript received August 24, 2009; revised November 28, 2009. Current version published March 24, 2010. This paper was approved by Guest Editor Masayuki Mizuno. This work was supported in part by the SRC under award 2008-HJ-1805. J. Keane, X. Wang, and C. H. Kim are with the Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN 55455 USA (e-mail: D. Persaud is with Intel Corporation. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier 10.1109/JSSC.2010.2040125 Fig. 1. HCI, BTI, and TDDB stress illustrated for NMOS and PMOS transistors, as well as for an inverter during standard operation.


  • Aging
  • Bias temperature instability
  • Circuit reliability
  • Dielectric breakdown
  • Digital measurements
  • Hot carriers


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