An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts

Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif

Research output: Chapter in Book/Report/Conference proceedingConference contribution

61 Scopus citations


With technology scaling, the trend for high performance integrated circuits is towards ever higher operating frequency, lower power supply voltages and higher power dissipation. This causes a dramatic increase in the currents being delivered through the on-chip power grid and is recognized in the International Technology Roadmap for Semiconductors as one of the difficult challenges. The addition of decoupling capacitances (decaps) is arguably the most powerful degree of freedom that a designer has for power-grid noise abatement and is becoming more important as technology scales. In this paper, we propose and demonstrate an algorithm for the automated placement and sizing of decaps in ASIC-like circuits. The adjoint sensitivity method is applied to calculate the first-order sensitivity of the power grid noise with respect to every decap. We propose a fast convolution technique based on piecewise linear (PWL) compressions of the original and adjoint waveforms. Experimental results show that power grid noise can be significantly reduced after a judicious optimization of decap placement, with little change of the total chip area.

Original languageEnglish (US)
Title of host publicationProceedings of the International Symposium on Physical Design
Number of pages6
StatePublished - Jan 1 2002
EventISPD-2002: International Symposium on Physical Design - Del Mar, CA, United States
Duration: Apr 7 2002Apr 10 2002


OtherISPD-2002: International Symposium on Physical Design
Country/TerritoryUnited States
CityDel Mar, CA


  • Adjoint sensitivity
  • ASICs
  • Decoupling capacitor
  • Optimization
  • Placement
  • Power grid noise


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