An aging model for current DACs, and its application to analyzing lifetime degradation in a wireline equalizer

Tonmoy Dhar, Jitesh Poojary, Ramesh Harjani, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

Abstract

Temporal degradation of transistors due to aging causes mismatch in the current mirror, a matching-critical building block of current digital to analog converters (IDACs). This mismatch induces non-linearity in IDAC behavior and can cause nonmonotonicity in the worst case. This paper performs an application-driven analysis of IDAC aging within a feed-forward equalizer (FFE) context. The work first models the effect of aging-induced mismatch over IDAC performance metrics and analyzes the performance shifts of IDACs over different topologies and input distributions. Next, the work illustrates how IDAC aging affects FFE behavior and presents novel schemes for FFE calibration to counter the impact of IDAC aging effectively.

Original languageEnglish (US)
Article number114912
JournalMicroelectronics Reliability
Volume142
DOIs
StatePublished - Mar 2023

Bibliographical note

Funding Information:
This work was supported in part by the National Science Foundation under award 1714805 .

Publisher Copyright:
© 2023 Elsevier Ltd

Keywords

  • Aging
  • Current mirror
  • Equalizer
  • IDAC
  • Mismatch

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