An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip

Mehdi Hatamian, Keshab K. Parhi

Research output: Contribution to journalArticle

17 Scopus citations

Abstract

This paper describes the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each; output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10 x 10 multiply-add modules are used in this chip. The chip contains 80 000 devices in an active area of 14 mm2. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5 × 109 multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed.

Original languageEnglish (US)
Pages (from-to)175-183
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume27
Issue number2
DOIs
StatePublished - Feb 1992

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