An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip

Mehdi Hatamian, Keshab K Parhi

Research output: Contribution to journalArticle

17 Citations (Scopus)

Abstract

This paper describes the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each; output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10 x 10 multiply-add modules are used in this chip. The chip contains 80 000 devices in an active area of 14 mm2. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5 × 109 multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed.

Original languageEnglish (US)
Pages (from-to)175-183
Number of pages9
JournalIEEE Journal of Solid-State Circuits
Volume27
Issue number2
DOIs
StatePublished - Jan 1 1992

Fingerprint

IIR filters
Digital filters
Clocks
FIR filters
Networks (circuits)
Experiments

Cite this

An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip. / Hatamian, Mehdi; Parhi, Keshab K.

In: IEEE Journal of Solid-State Circuits, Vol. 27, No. 2, 01.01.1992, p. 175-183.

Research output: Contribution to journalArticle

@article{4f673c7356634f019cacda18b166a827,
title = "An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip",
abstract = "This paper describes the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each; output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10 x 10 multiply-add modules are used in this chip. The chip contains 80 000 devices in an active area of 14 mm2. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5 × 109 multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed.",
author = "Mehdi Hatamian and Parhi, {Keshab K}",
year = "1992",
month = "1",
day = "1",
doi = "10.1109/4.127340",
language = "English (US)",
volume = "27",
pages = "175--183",
journal = "IEEE Journal of Solid-State Circuits",
issn = "0018-9200",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "2",

}

TY - JOUR

T1 - An 85-MHz Fourth-Order Programmable IIR Digital Filter Chip

AU - Hatamian, Mehdi

AU - Parhi, Keshab K

PY - 1992/1/1

Y1 - 1992/1/1

N2 - This paper describes the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each; output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10 x 10 multiply-add modules are used in this chip. The chip contains 80 000 devices in an active area of 14 mm2. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5 × 109 multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed.

AB - This paper describes the design and VLSI implementation of a single-chip 85-MHz fourth-order infinite impulse response (IIR) digital filter chip fabricated in 0.9-μm CMOS technology. The coefficient and input data word lengths of the filter are 10 b each; output data word length is 15 b. The coefficients are fully programmable. The chip can be programmed to implement any IIR filter from first to fourth order or an FIR filter up to 16th order at sample rates up to 85 MHz. A total of seventeen 10 x 10 multiply-add modules are used in this chip. The chip contains 80 000 devices in an active area of 14 mm2. It dissipates 2.2 W at 85-MHz clock rate and performs over 1.5 × 109 multiply-add operations per second. The underlying filtering algorithm, chip architecture, circuit and layout design, speed issues, and test results are described. The results of an E-beam probing experiment on packaged chips at 100-MHz clock rates are also presented and discussed.

UR - http://www.scopus.com/inward/record.url?scp=0026821944&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0026821944&partnerID=8YFLogxK

U2 - 10.1109/4.127340

DO - 10.1109/4.127340

M3 - Article

VL - 27

SP - 175

EP - 183

JO - IEEE Journal of Solid-State Circuits

JF - IEEE Journal of Solid-State Circuits

SN - 0018-9200

IS - 2

ER -