An 8-bit 22-MHz recycling two-step ASIC ADC with integrating sample and hold

Somsak Wongkittikriwon, Stanley G. Burns

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A recycling two-step architecture with a very low input current comparator is used to implement an 8-bit ADC with an integrating S/H mat yields a 22 Msps conversion rate with a 10 MHz input. This twostep recycling architecture makes use of a novel switch circuit design reducing the number of components required for the complete ADC. The ADC is realized using 900 transistors on 2-metal, fT = 8.5 GHz, npn BIT ASICs.

Original languageEnglish (US)
Title of host publication1992 Proceedings of the 35th Midwest Symposium on Circuits and Systems
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages839-842
Number of pages4
ISBN (Electronic)0780305108
DOIs
StatePublished - Jan 1 1992
Externally publishedYes
Event35th Midwest Symposium on Circuits and Systems, MWSCAS 1992 - Washington, United States
Duration: Aug 9 1992Aug 12 1992

Publication series

NameMidwest Symposium on Circuits and Systems
Volume1992-August
ISSN (Print)1548-3746

Conference

Conference35th Midwest Symposium on Circuits and Systems, MWSCAS 1992
CountryUnited States
CityWashington
Period8/9/928/12/92

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