All-digital PLL frequency and phase noise degradation measurements using simple on-chip monitoring circuits

Gyusung Park, Minsu Kim, Chris H. Kim, Bongjin Kim, Vijay Reddy

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

Using simple on-chip monitoring circuits, we precisely characterized the impact of hot carrier injection and bias temperature instability on frequency and phase noise degradation of a 65nm all-digital PLL circuit. Experimental data shows that PLL phase noise degrades with aging even though the output frequency is maintained constant due to the PLL feedback operation. Results show that applying high temperature annealing can recover most of the phase noise degradation.

Original languageEnglish (US)
Title of host publication2018 IEEE International Reliability Physics Symposium, IRPS 2018
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages5C.21-5C.26
ISBN (Electronic)9781538654798
DOIs
StatePublished - May 25 2018
Event2018 IEEE International Reliability Physics Symposium, IRPS 2018 - Burlingame, United States
Duration: Mar 11 2018Mar 15 2018

Publication series

NameIEEE International Reliability Physics Symposium Proceedings
Volume2018-March
ISSN (Print)1541-7026

Other

Other2018 IEEE International Reliability Physics Symposium, IRPS 2018
CountryUnited States
CityBurlingame
Period3/11/183/15/18

Keywords

  • Bias temperature instability (BTI)
  • hot carrier injection (HCI)
  • phase noise
  • phase-locked loop (PLL)
  • thermal recovery

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