ALIGN: A System for Automating Analog Layout

Tonmoy Dhar, Kishor Kunal, Yaguang Li, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar

Research output: Contribution to journalArticlepeer-review

1 Scopus citations


ALIGN (“Analog Layout, Intelligently Generated from Netlists”) is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits.

Original languageEnglish (US)
Article number9279310
Pages (from-to)8-18
Number of pages11
JournalIEEE Design and Test
Issue number2
StatePublished - Apr 2021

Bibliographical note

Funding Information:
This work was supported in part by the DARPA IDEA program under SPAWAR Contract N660011824048.

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