AI Computing in Light of 2.5D Interconnect Roadmap: Big-Little Chiplets for In-memory Acceleration

Zhenyu Wang, Gopikrishnan Raveendran Nair, Gokul Krishnan, Sumit K. Mandal, Ninoo Cherian, Jae Sun Seo, Chaitali Chakrabarti, Umit Y. Ogras, Yu Cao

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Scopus citations

Abstract

The demands on bandwidth, latency and energy efficiency are ever increasing in AI computing. Chiplets, connected by 2. 5D interconnect, promise a scalable platform to meet such needs. We present a pathfinding study to bridge AI algorithms with the chiplet architecture, covering in memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. This study is enabled by our newly developed benchmarking tool, SIAM. We perform simulations on representative algorithms (DNNs, transformers and GCNs). Particular contributions include: (1) A roadmap of 2. 5D interconnect for technological exploration; (2) A generic mapping and optimization methodology that reveals various bandwidth needs in AI computing, where the evolution of 2.5D interconnect can or cannot support; (3) A big-little chiplet architecture that matches the non-uniform nature of AI algorithms and achieves >100× improvement in EDP. Overall, heterogeneous big-little chiplets with 2. 5D interconnect advance AI computing to the next level of data movement and computing efficiency.

Original languageEnglish (US)
Title of host publication2022 International Electron Devices Meeting, IEDM 2022
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages2361-2364
Number of pages4
ISBN (Electronic)9781665489591
DOIs
StatePublished - 2022
Externally publishedYes
Event2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States
Duration: Dec 3 2022Dec 7 2022

Publication series

NameTechnical Digest - International Electron Devices Meeting, IEDM
Volume2022-December
ISSN (Print)0163-1918

Conference

Conference2022 International Electron Devices Meeting, IEDM 2022
Country/TerritoryUnited States
CitySan Francisco
Period12/3/2212/7/22

Bibliographical note

Funding Information:
This work was partially supported by C-BRIC, one of six centers in JUMP, a Semiconductor Research Corporation (SRC) program sponsored by DARPA.

Publisher Copyright:
© 2022 IEEE.

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