Abstract
The demands on bandwidth, latency and energy efficiency are ever increasing in AI computing. Chiplets, connected by 2. 5D interconnect, promise a scalable platform to meet such needs. We present a pathfinding study to bridge AI algorithms with the chiplet architecture, covering in memory computing (IMC), network-on-package (NoP), and heterogeneous architecture. This study is enabled by our newly developed benchmarking tool, SIAM. We perform simulations on representative algorithms (DNNs, transformers and GCNs). Particular contributions include: (1) A roadmap of 2. 5D interconnect for technological exploration; (2) A generic mapping and optimization methodology that reveals various bandwidth needs in AI computing, where the evolution of 2.5D interconnect can or cannot support; (3) A big-little chiplet architecture that matches the non-uniform nature of AI algorithms and achieves >100× improvement in EDP. Overall, heterogeneous big-little chiplets with 2. 5D interconnect advance AI computing to the next level of data movement and computing efficiency.
Original language | English (US) |
---|---|
Title of host publication | 2022 International Electron Devices Meeting, IEDM 2022 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 2361-2364 |
Number of pages | 4 |
ISBN (Electronic) | 9781665489591 |
DOIs | |
State | Published - 2022 |
Externally published | Yes |
Event | 2022 International Electron Devices Meeting, IEDM 2022 - San Francisco, United States Duration: Dec 3 2022 → Dec 7 2022 |
Publication series
Name | Technical Digest - International Electron Devices Meeting, IEDM |
---|---|
Volume | 2022-December |
ISSN (Print) | 0163-1918 |
Conference
Conference | 2022 International Electron Devices Meeting, IEDM 2022 |
---|---|
Country/Territory | United States |
City | San Francisco |
Period | 12/3/22 → 12/7/22 |
Bibliographical note
Publisher Copyright:© 2022 IEEE.