TY - GEN
T1 - Addressing thermal and power delivery bottlenecks in 3D circuits
AU - Sapatnekar, Sachin S.
PY - 2009
Y1 - 2009
N2 - The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per package pin, leading to possible power delivery bottlenecks. This paper presents an overview of the challenges and solutions in the domain of addressing these two issues in 3D integrated circuits.
AB - The enhanced packing densities facilitated by 3D integrated circuit technology also has an unwanted side-effect, in the form of increasing the amount of current per unit footprint of the chip, as compared to a 2D design. This has ramifications on two critical issues: firstly, it means that more heat is generated per unit footprint, potentially leading to thermal problems, and secondly, more current must be supplied per package pin, leading to possible power delivery bottlenecks. This paper presents an overview of the challenges and solutions in the domain of addressing these two issues in 3D integrated circuits.
UR - https://www.scopus.com/pages/publications/64549151567
UR - https://www.scopus.com/pages/publications/64549151567#tab=citedBy
U2 - 10.1109/ASPDAC.2009.4796518
DO - 10.1109/ASPDAC.2009.4796518
M3 - Conference contribution
AN - SCOPUS:64549151567
SN - 9781424427482
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 423
EP - 428
BT - Proceedings of the ASP-DAC 2009
T2 - Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Y2 - 19 January 2009 through 22 January 2009
ER -