Negative bias temperature instability (NBTI) in pMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guardbanding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.
|Original language||English (US)|
|Number of pages||12|
|Journal||IEEE Transactions on Very Large Scale Integration (VLSI) Systems|
|State||Published - Apr 2011|
Bibliographical noteFunding Information:
We gratefully acknowledge Elihu Boldt, Francesc Ferrer, Haim Goldberg, Tom McCauley, Andreas Ringwald, Subir Sarkar, Peter Tinyakov, and Alan Watson for useful their discussions and email correspondence. We further acknowledge Alan Watson for his kind permission to use the Haverah Park data. The work of D. F. T. was performed under the auspices of the US DOE (NNSA), by University of California Lawrence Livermore National Laboratory under contract W-7405-Eng-48. The research of S. R. and L. A. A was partially supported by the US National Science Foundation (NSF) under grant PHY-0140407.
- CMOS digital integrated circuits
- Circuit synthesis
- Digital circuits
- High-K gate dielectrics
- Negative bias temperature instability
- Niobium compounds
- Titanium compounds