TY - JOUR
T1 - Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits
AU - Kumar, Sanjay V.
AU - Kim, Chris H.
AU - Sapatnekar, Sachin S
PY - 2011/4/1
Y1 - 2011/4/1
N2 - Negative bias temperature instability (NBTI) in pMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guardbanding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.
AB - Negative bias temperature instability (NBTI) in pMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent introduction of Hf-based high-k dielectrics for gate leakage reduction, positive bias temperature instability (PBTI), the dual effect in nMOS transistors, has also reached significant levels. Consequently, designs are required to build in substantial guardbands in order to guarantee reliable operation over the lifetime of a chip, and these involve large area and power overheads. In this paper, we begin by proposing the use of adaptive body bias (ABB) and adaptive supply voltage (ASV) to maintain optimal performance of an aged circuit, and demonstrate its advantages over a guardbanding technique such as synthesis. We then present a hybrid approach, utilizing the merits of both ABB and synthesis, to ensure that the resultant circuit meets the performance constraints over its lifetime, and has a minimal area and power overhead, as compared with a nominally designed circuit.
KW - Aging
KW - CMOS digital integrated circuits
KW - Circuit synthesis
KW - Degradation
KW - Digital circuits
KW - High-K gate dielectrics
KW - MOSFETs
KW - Negative bias temperature instability
KW - Niobium compounds
KW - Titanium compounds
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U2 - 10.1109/TVLSI.2009.2036628
DO - 10.1109/TVLSI.2009.2036628
M3 - Article
AN - SCOPUS:79953092815
VL - 19
SP - 603
EP - 614
JO - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
JF - IEEE Transactions on Very Large Scale Integration (VLSI) Systems
SN - 1063-8210
IS - 4
M1 - 5371864
ER -