Adaptive Directional Lifting Wavelet Transform VLSI Architecture

Sangho Yun, Gerald E Sobelman, Xiaofang Zhou

Research output: Contribution to journalArticle

Abstract

This paper presents an efficient VLSI architecture of the 2-D wavelet transform for the adaptive directional lifting (ADL) scheme in image coding. To avoid accumulating errors from irrational wavelet transform coefficients, algebraic integers with appropriate input scaling parameters are used. A two-parallel architecture with zigzag processing of the image stream is used to increase the throughput. In a 45-nm CMOS technology, the synthesis results indicate that the proposed architectures for the Daub-4 and 5/3 wavelets can operate at a clock frequency of about 250 MHz with an estimated throughput of 4 Gb/s.

Original languageEnglish (US)
Pages (from-to)551-559
Number of pages9
JournalJournal of Signal Processing Systems
Volume91
Issue number5
DOIs
StatePublished - May 15 2019

Fingerprint

VLSI Architecture
Wavelet transforms
Wavelet Transform
Throughput
Lifting Scheme
Algebraic integer
Image Coding
Parallel architectures
Zigzag
Parallel Architectures
Image coding
Clocks
Wavelets
Scaling
Synthesis
Coefficient
Processing
Architecture

Keywords

  • Adaptive directional lifting
  • Algebraic integers
  • Image coding
  • Image compression
  • Lifting wavelet transform

Cite this

Adaptive Directional Lifting Wavelet Transform VLSI Architecture. / Yun, Sangho; Sobelman, Gerald E; Zhou, Xiaofang.

In: Journal of Signal Processing Systems, Vol. 91, No. 5, 15.05.2019, p. 551-559.

Research output: Contribution to journalArticle

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