Accurate estimation of global buffer delay within a floorplan

Charles J. Alpert, Jiang Hu, Sachin S. Sapatnekar, C. N. Sze

Research output: Contribution to journalArticlepeer-review

23 Scopus citations


Closed-form expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently have large blocks that make the ideal buffer-insertion solution unrealizable. The theory of Otten (ACM/IEEE Intl. Symp. Physical Design, p. 104, 1998) is extended to show how one can model the blocks into a simple delay-estimation technique that applies to both two-pin and multipin nets. Even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer-insertion solution. Potential applications include wire planning, timing analysis during floorplanning, or global routing. The authors' experiments show that their approach accurately predicts delay when compared to constructing a realizable buffer insertion with multiple buffer types.

Original languageEnglish (US)
Pages (from-to)1140-1146
Number of pages7
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number6
StatePublished - Jun 2006

Bibliographical note

Funding Information:
Manuscript received August 29, 2004; revised March 29, 2005. This work was supported in part by the Semiconductor Research Corporation (SRC) under Contract 2003-TJ-1124. This paper was recommended by Associate Editor M. D. F. Wong.


  • Delay estimation
  • Design automation
  • Integrated circuit interconnections
  • Integrated circuit layout
  • RC circuits
  • Repeaters
  • Very large scale integration


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