Accelerating Deterministic Bit-Stream Computing with Resolution Splitting

M. Hassan Najafi, S. Rasoul Faraji, Bingzhe Li, David J Lilja, Kia Bazargan

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Deterministic approaches to stochastic computing (SC) have been recently proposed to produce completely accurate results with stochastic logic. Long processing time is the main limitation of these methods when a deterministic zero error rate output is expected. For instance, when multiplying two n-bit precision input values, a processing time of 22n cycles is required. This long processing time makes the current deterministic approaches of SC inefficient for many applications. In this work, we propose an acceleration method based on resolution splitting to mitigate this long latency. The result is an exponential reduction in the processing time at the cost of some increase in the hardware area. The exponential reduction in the processing time results in a significant reduction in energy consumption. Synthesis results show that for the common 2-input multiplier, the proposed design decreases the energy consumption more than 2000× compared to the prior state-of-the-art deterministic bit-stream-based design.

Original languageEnglish (US)
Title of host publicationProceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019
PublisherIEEE Computer Society
Pages157-162
Number of pages6
ISBN (Electronic)9781728103921
DOIs
StatePublished - Apr 23 2019
Event20th International Symposium on Quality Electronic Design, ISQED 2019 - Santa Clara, United States
Duration: Mar 6 2019Mar 7 2019

Publication series

NameProceedings - International Symposium on Quality Electronic Design, ISQED
Volume2019-March
ISSN (Print)1948-3287
ISSN (Electronic)1948-3295

Conference

Conference20th International Symposium on Quality Electronic Design, ISQED 2019
CountryUnited States
CitySanta Clara
Period3/6/193/7/19

Fingerprint

Processing
Energy utilization
Hardware

Keywords

  • Stochastic Computing
  • deterministic bit-stream computing
  • performance enhancement
  • resolution splitting

Cite this

Najafi, M. H., Faraji, S. R., Li, B., Lilja, D. J., & Bazargan, K. (2019). Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019 (pp. 157-162). [8697443] (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March). IEEE Computer Society. https://doi.org/10.1109/ISQED.2019.8697443

Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. / Najafi, M. Hassan; Faraji, S. Rasoul; Li, Bingzhe; Lilja, David J; Bazargan, Kia.

Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. p. 157-162 8697443 (Proceedings - International Symposium on Quality Electronic Design, ISQED; Vol. 2019-March).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Najafi, MH, Faraji, SR, Li, B, Lilja, DJ & Bazargan, K 2019, Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. in Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019., 8697443, Proceedings - International Symposium on Quality Electronic Design, ISQED, vol. 2019-March, IEEE Computer Society, pp. 157-162, 20th International Symposium on Quality Electronic Design, ISQED 2019, Santa Clara, United States, 3/6/19. https://doi.org/10.1109/ISQED.2019.8697443
Najafi MH, Faraji SR, Li B, Lilja DJ, Bazargan K. Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. In Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society. 2019. p. 157-162. 8697443. (Proceedings - International Symposium on Quality Electronic Design, ISQED). https://doi.org/10.1109/ISQED.2019.8697443
Najafi, M. Hassan ; Faraji, S. Rasoul ; Li, Bingzhe ; Lilja, David J ; Bazargan, Kia. / Accelerating Deterministic Bit-Stream Computing with Resolution Splitting. Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019. IEEE Computer Society, 2019. pp. 157-162 (Proceedings - International Symposium on Quality Electronic Design, ISQED).
@inproceedings{96f540c8d5964bea9e31a11af4bcc65a,
title = "Accelerating Deterministic Bit-Stream Computing with Resolution Splitting",
abstract = "Deterministic approaches to stochastic computing (SC) have been recently proposed to produce completely accurate results with stochastic logic. Long processing time is the main limitation of these methods when a deterministic zero error rate output is expected. For instance, when multiplying two n-bit precision input values, a processing time of 22n cycles is required. This long processing time makes the current deterministic approaches of SC inefficient for many applications. In this work, we propose an acceleration method based on resolution splitting to mitigate this long latency. The result is an exponential reduction in the processing time at the cost of some increase in the hardware area. The exponential reduction in the processing time results in a significant reduction in energy consumption. Synthesis results show that for the common 2-input multiplier, the proposed design decreases the energy consumption more than 2000× compared to the prior state-of-the-art deterministic bit-stream-based design.",
keywords = "Stochastic Computing, deterministic bit-stream computing, performance enhancement, resolution splitting",
author = "Najafi, {M. Hassan} and Faraji, {S. Rasoul} and Bingzhe Li and Lilja, {David J} and Kia Bazargan",
year = "2019",
month = "4",
day = "23",
doi = "10.1109/ISQED.2019.8697443",
language = "English (US)",
series = "Proceedings - International Symposium on Quality Electronic Design, ISQED",
publisher = "IEEE Computer Society",
pages = "157--162",
booktitle = "Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019",

}

TY - GEN

T1 - Accelerating Deterministic Bit-Stream Computing with Resolution Splitting

AU - Najafi, M. Hassan

AU - Faraji, S. Rasoul

AU - Li, Bingzhe

AU - Lilja, David J

AU - Bazargan, Kia

PY - 2019/4/23

Y1 - 2019/4/23

N2 - Deterministic approaches to stochastic computing (SC) have been recently proposed to produce completely accurate results with stochastic logic. Long processing time is the main limitation of these methods when a deterministic zero error rate output is expected. For instance, when multiplying two n-bit precision input values, a processing time of 22n cycles is required. This long processing time makes the current deterministic approaches of SC inefficient for many applications. In this work, we propose an acceleration method based on resolution splitting to mitigate this long latency. The result is an exponential reduction in the processing time at the cost of some increase in the hardware area. The exponential reduction in the processing time results in a significant reduction in energy consumption. Synthesis results show that for the common 2-input multiplier, the proposed design decreases the energy consumption more than 2000× compared to the prior state-of-the-art deterministic bit-stream-based design.

AB - Deterministic approaches to stochastic computing (SC) have been recently proposed to produce completely accurate results with stochastic logic. Long processing time is the main limitation of these methods when a deterministic zero error rate output is expected. For instance, when multiplying two n-bit precision input values, a processing time of 22n cycles is required. This long processing time makes the current deterministic approaches of SC inefficient for many applications. In this work, we propose an acceleration method based on resolution splitting to mitigate this long latency. The result is an exponential reduction in the processing time at the cost of some increase in the hardware area. The exponential reduction in the processing time results in a significant reduction in energy consumption. Synthesis results show that for the common 2-input multiplier, the proposed design decreases the energy consumption more than 2000× compared to the prior state-of-the-art deterministic bit-stream-based design.

KW - Stochastic Computing

KW - deterministic bit-stream computing

KW - performance enhancement

KW - resolution splitting

UR - http://www.scopus.com/inward/record.url?scp=85065182253&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85065182253&partnerID=8YFLogxK

U2 - 10.1109/ISQED.2019.8697443

DO - 10.1109/ISQED.2019.8697443

M3 - Conference contribution

T3 - Proceedings - International Symposium on Quality Electronic Design, ISQED

SP - 157

EP - 162

BT - Proceedings of the 20th International Symposium on Quality Electronic Design, ISQED 2019

PB - IEEE Computer Society

ER -