TY - GEN
T1 - A workload-aware neuromorphic controller for dynamic power and thermal management
AU - Sinha, Saurabh
AU - Suh, Jounghyuk
AU - Bakkaloglu, Bertan
AU - Cao, Yu
PY - 2011
Y1 - 2011
N2 - A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and preemptively regulates supply voltage and frequency. Our specific contributions include: (1) implementation of a digital and analog version of the controller in 45nm CMOS technology, resulting in 3% performance hit with a power overhead in the range of 10-150 microwatts from the controller circuit, (2) higher prediction accuracy compared to a software based OS-governed DVFS scheme, reducing wasted power and improving error margins, (3) power savings of up to 52% and improvement of up to 15% compared to the OS based scheme, (4) implementing DVFS when the processor is memory bandwidth limited for additional savings and (4) accurate temperature prediction to proactively implement DVFS and prevent CPU shutdown.The digital design has minimal power overhead and is more reconfigurable, while analog design is better suited for nonlinear and complex computational tasks.
AB - A workload-aware low-power neuromorphic controller for dynamic power and thermal management in VLSI systems is presented. The neuromorphic controller predicts future workload and temperature values based on the past values and preemptively regulates supply voltage and frequency. Our specific contributions include: (1) implementation of a digital and analog version of the controller in 45nm CMOS technology, resulting in 3% performance hit with a power overhead in the range of 10-150 microwatts from the controller circuit, (2) higher prediction accuracy compared to a software based OS-governed DVFS scheme, reducing wasted power and improving error margins, (3) power savings of up to 52% and improvement of up to 15% compared to the OS based scheme, (4) implementing DVFS when the processor is memory bandwidth limited for additional savings and (4) accurate temperature prediction to proactively implement DVFS and prevent CPU shutdown.The digital design has minimal power overhead and is more reconfigurable, while analog design is better suited for nonlinear and complex computational tasks.
UR - http://www.scopus.com/inward/record.url?scp=80052123455&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=80052123455&partnerID=8YFLogxK
U2 - 10.1109/AHS.2011.5963936
DO - 10.1109/AHS.2011.5963936
M3 - Conference contribution
AN - SCOPUS:80052123455
SN - 9781457705984
T3 - Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011
SP - 200
EP - 207
BT - Proceedings of the 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011
T2 - 2011 NASA/ESA Conference on Adaptive Hardware and Systems, AHS 2011
Y2 - 6 June 2011 through 9 June 2011
ER -