A voltage scalable 0.26V, 64kb 8T SRAM with vmin lowering techniques and deep sleep mode

Tae Hyoung Kim; Jason Liu; Chris H. Kim

doi:10.1109/CICC.2008.4672106

A voltage scalable 0.26V, 64kb 8T SRAM with v_min lowering techniques and deep sleep mode

Tae Hyoung Kim
, Jason Liu
, Chris H. Kim

Electrical and Computer Engineering

Research output: Contribution to journal › Conference article › peer-review

13 Scopus citations

Abstract

A voltage scalable 0.26V, 64kb 8T SRAM with 512 cells per bitline is implemented in a 130nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower V_min down to 0.26V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode minimize the active and standby leakage power consumption.

Original language	English (US)
Article number	4672106
Pages (from-to)	407-410
Number of pages	4
Journal	Proceedings of the Custom Integrated Circuits Conference
DOIs	https://doi.org/10.1109/CICC.2008.4672106
State	Published - 2008
Event	IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States Duration: Sep 21 2008 → Sep 24 2008

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10.1109/CICC.2008.4672106

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abstract = "A voltage scalable 0.26V, 64kb 8T SRAM with 512 cells per bitline is implemented in a 130nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower Vmin down to 0.26V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode minimize the active and standby leakage power consumption.",

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year = "2008",

doi = "10.1109/CICC.2008.4672106",

language = "English (US)",

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journal = "Proceedings of the Custom Integrated Circuits Conference",

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note = "IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 ; Conference date: 21-09-2008 Through 24-09-2008",

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AU - Liu, Jason

AU - Kim, Chris H.

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AB - A voltage scalable 0.26V, 64kb 8T SRAM with 512 cells per bitline is implemented in a 130nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower Vmin down to 0.26V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode minimize the active and standby leakage power consumption.

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DO - 10.1109/CICC.2008.4672106

M3 - Conference article

AN - SCOPUS:57849085783

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JF - Proceedings of the Custom Integrated Circuits Conference

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ER -

A voltage scalable 0.26V, 64kb 8T SRAM with v_min lowering techniques and deep sleep mode

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