A voltage scalable 0.26V, 64kb 8T SRAM with 512 cells per bitline is implemented in a 130nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower Vmin down to 0.26V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode minimize the active and standby leakage power consumption.
|Original language||English (US)|
|Number of pages||4|
|Journal||Proceedings of the Custom Integrated Circuits Conference|
|State||Published - Dec 26 2008|
|Event||IEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States|
Duration: Sep 21 2008 → Sep 24 2008