A voltage scalable 0.26V, 64kb 8T SRAM with vmin lowering techniques and deep sleep mode

Tae Hyoung Kim, Jason Liu, Chris H. Kim

Research output: Contribution to journalConference articlepeer-review

11 Scopus citations

Abstract

A voltage scalable 0.26V, 64kb 8T SRAM with 512 cells per bitline is implemented in a 130nm CMOS process. Reverse short channel effect was utilized to improve cell write margin and read performance. A marginal bitline leakage compensation scheme was used during read operation to lower Vmin down to 0.26V. Floating write bitline and read bitline, auto wordline pulse width control, and a deep sleep mode minimize the active and standby leakage power consumption.

Original languageEnglish (US)
Article number4672106
Pages (from-to)407-410
Number of pages4
JournalProceedings of the Custom Integrated Circuits Conference
DOIs
StatePublished - Dec 26 2008
EventIEEE 2008 Custom Integrated Circuits Conference, CICC 2008 - San Jose, CA, United States
Duration: Sep 21 2008Sep 24 2008

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