Abstract
In this paper we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising.
| Original language | English (US) |
|---|---|
| Title of host publication | IEEE/ACM International Conference on Computer Aided Design |
| Subtitle of host publication | A Conference for the EE CAD Professional, ICCAD 2000 |
| Publisher | Institute of Electrical and Electronics Engineers Inc. |
| Pages | 99-103 |
| Number of pages | 5 |
| ISBN (Electronic) | 0780364457 |
| DOIs | |
| State | Published - 2000 |
| Event | IEEE/ACM International Conference on Computer Aided Design, ICCAD 2000 - San Jose, United States Duration: Nov 5 2000 → Nov 9 2000 |
Publication series
| Name | IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD |
|---|---|
| Volume | 2000-January |
| ISSN (Print) | 1092-3152 |
Other
| Other | IEEE/ACM International Conference on Computer Aided Design, ICCAD 2000 |
|---|---|
| Country/Territory | United States |
| City | San Jose |
| Period | 11/5/00 → 11/9/00 |
Bibliographical note
Publisher Copyright:© 2000 IEEE.