TY - GEN
T1 - A timing-constrained algorithm for simultaneous global routing of multiple nets
AU - Hu, Jiang
AU - Sapatnekar, Sachin S.
PY - 2000/1/1
Y1 - 2000/1/1
N2 - In this paper we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising.
AB - In this paper we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising.
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U2 - 10.1109/ICCAD.2000.896457
DO - 10.1109/ICCAD.2000.896457
M3 - Conference contribution
AN - SCOPUS:0034478158
T3 - IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
SP - 99
EP - 103
BT - IEEE/ACM International Conference on Computer Aided Design
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - IEEE/ACM International Conference on Computer Aided Design, ICCAD 2000
Y2 - 5 November 2000 through 9 November 2000
ER -