A timing-constrained algorithm for simultaneous global routing of multiple nets

Research output: Chapter in Book/Report/Conference proceedingConference contribution

47 Scopus citations

Abstract

In this paper we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising.

Original languageEnglish (US)
Title of host publicationIEEE/ACM International Conference on Computer Aided Design
Subtitle of host publicationA Conference for the EE CAD Professional, ICCAD 2000
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages99-103
Number of pages5
ISBN (Electronic)0780364457
DOIs
StatePublished - Jan 1 2000
EventIEEE/ACM International Conference on Computer Aided Design, ICCAD 2000 - San Jose, United States
Duration: Nov 5 2000Nov 9 2000

Publication series

NameIEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD
Volume2000-January
ISSN (Print)1092-3152

Other

OtherIEEE/ACM International Conference on Computer Aided Design, ICCAD 2000
CountryUnited States
CitySan Jose
Period11/5/0011/9/00

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