A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS

Fang Li Yuan; Rakesh Kumar Palani; Sina Basir-Kazeruni; Hundo Shih; Anindya Saha; Ramesh Harjani; Dejan Marković

doi:10.1109/VLSIC.2015.7231245

A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS

Fang Li Yuan, Rakesh Kumar Palani, Sina Basir-Kazeruni, Hundo Shih, Anindya Saha, Ramesh Harjani, Dejan Marković

Electrical and Computer Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Scopus citations

Abstract

A blind classification SoC for cognitive radios, featuring multi-signal channelization, 16-core dynamic parallelism-frequency scaling and GALS-based multithreading, is realized in 40nm CMOS. Targeting ≥95% detection probability and ≤ 0.5% false-alarm rate, the SoC achieves a throughput-insensitive energy efficiency of 11.9-13.6GOPS/mW for multiple 7.8-125MHz bandwidth-agnostic signals in a 500MHz channel. The SoC shows 2.1x lower energy, >2.7x less efficiency variation, 1.2x baseband area and up to 4x processing time reduction compared to prior work. Throughput-matched scheduling of spatial resources enables operation at peak energy efficiency without the need for any voltage adjustment.

Original language	English (US)
Title of host publication	2015 Symposium on VLSI Circuits, VLSI Circuits 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	C150-C151
ISBN (Electronic)	9784863485020
DOIs	https://doi.org/10.1109/VLSIC.2015.7231245
State	Published - Aug 31 2015
Event	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015 - Kyoto, Japan Duration: Jun 17 2015 → Jun 19 2015

Publication series

Name	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
Volume	2015-August

Other

Other	29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015
Country/Territory	Japan
City	Kyoto
Period	6/17/15 → 6/19/15

Bibliographical note

Publisher Copyright:
© 2015 JSAP.

Publisher link

10.1109/VLSIC.2015.7231245

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Yuan, F. L., Palani, R. K., Basir-Kazeruni, S., Shih, H., Saha, A., Harjani, R., & Marković, D. (2015). A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015 (pp. C150-C151). Article 7231245 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIC.2015.7231245

A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS. / Yuan, Fang Li; Palani, Rakesh Kumar; Basir-Kazeruni, Sina et al.
2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. C150-C151 7231245 (IEEE Symposium on VLSI Circuits, Digest of Technical Papers; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Yuan, FL, Palani, RK, Basir-Kazeruni, S, Shih, H, Saha, A, Harjani, R & Marković, D 2015, A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS. in 2015 Symposium on VLSI Circuits, VLSI Circuits 2015., 7231245, IEEE Symposium on VLSI Circuits, Digest of Technical Papers, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., pp. C150-C151, 29th Annual Symposium on VLSI Circuits, VLSI Circuits 2015, Kyoto, Japan, 6/17/15. https://doi.org/10.1109/VLSIC.2015.7231245

Yuan FL, Palani RK, Basir-Kazeruni S, Shih H, Saha A, Harjani R et al. A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS. In 2015 Symposium on VLSI Circuits, VLSI Circuits 2015. Institute of Electrical and Electronics Engineers Inc. 2015. p. C150-C151. 7231245. (IEEE Symposium on VLSI Circuits, Digest of Technical Papers). doi: 10.1109/VLSIC.2015.7231245

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abstract = "A blind classification SoC for cognitive radios, featuring multi-signal channelization, 16-core dynamic parallelism-frequency scaling and GALS-based multithreading, is realized in 40nm CMOS. Targeting ≥95% detection probability and ≤ 0.5% false-alarm rate, the SoC achieves a throughput-insensitive energy efficiency of 11.9-13.6GOPS/mW for multiple 7.8-125MHz bandwidth-agnostic signals in a 500MHz channel. The SoC shows 2.1x lower energy, >2.7x less efficiency variation, 1.2x baseband area and up to 4x processing time reduction compared to prior work. Throughput-matched scheduling of spatial resources enables operation at peak energy efficiency without the need for any voltage adjustment.",

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A throughput-agnostic 11.9-13.6GOPS/mW multi-signal classification SoC for cognitive radios in 40nm CMOS

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