A theoretical approach to estimation of bounds on power consumption in digital multipliers

Keyphrases

• Power Consumption 100%
• State Transition Diagram 100%
• Digital multiplier 100%
• Subcircuit 66%
• Energy Value 33%
• Tight 33%
• Average Power 33%
• Average Power Consumption 33%
• Binary Tree 33%
• Minimum Energy 33%
• Bit Level 33%
• Heat Sink 33%
• Switching Activity 33%
• Consumption Values 33%
• P-bits 33%
• Pipelined multiplier 33%
• Baugh-Wooley multiplier 33%
• Tree multiplier 33%
• Wallace Tree multiplier 33%
• Upper-lower Bounds 33%
• Portable Applications 33%
• Battery Life 33%
• Theoretical Upper Bound 33%
• One-state Reality 33%

Engineering

• Electric Power Utilization 100%
• State Transition Diagram 75%
• Average Power 50%
• Subcircuit 50%
• Experimental Result 25%
• Switching Activity 25%
• Battery Life 25%
• Portable Application 25%
• Binary Tree 25%
• Calorific Value 25%

Computer Science

• Power Consumption 100%
• State Transition Diagram 100%
• Pipelining 33%
• Average Power Consumption 33%
• Binary Tree 33%
• Experimental Result 33%
• Switching Activity 33%
• Portable Application 33%